From bd4defccd12480d92e6242d097e122dd6c3c1f8f Mon Sep 17 00:00:00 2001
From: Santosh Male <santosh.male@intel.com>
Date: Thu, 3 Aug 2023 18:03:41 +0000
Subject: [PATCH] boards: arm64: Added board dts files

Updated board dts files for socdk and simics vp
with XGMAC and network configuration.

Signed-off-by: Santosh Male <santosh.male@intel.com>
---
 .../intel_socfpga_agilex5_socdk.dts           | 26 ++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts
index 701401f569b..d2f6c4370a3 100644
--- a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts
+++ b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Intel Corporation.
+ * Copyright (c) 2024, Intel Corporation.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,3 +34,27 @@
 	status = "okay";
 	current-speed = <115200>;
 };
+
+&xgmac0 {
+	full-duplex-mode-en;
+	num-dma-ch   = <1>;
+	num-tx-queues = <1>;
+	num-rx-queues = <1>;
+	num-tc = <1>;
+	dma-ch-rdrl = <128>;
+	dma-ch-tdrl = <128>;
+	max-speed = <1000>;
+	max-frame-size = <9018>;
+	jumbo-pkt-en;
+	zephyr,random-mac-address;
+	phy-handle = <&phy0>;
+};
+
+&mdio0  {
+	csr-clock-indx = <4>;
+
+	phy0: phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0>;
+	};
+};