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drivers: serial: uart_xlnx_uartlite: set irq flags per device tree

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PG142 from AMD specifically says the uartlite IP generates a
"rising-edge sensitive interrupt" when interrupts are enabled. When
using this IP on a ZynqMP platform with
CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get
configured correctly to detect these interrupts. Update driver to heed
the flags set by the interrupts property in the device tree.

Signed-off-by: Michael Estes <michael.estes@byteserv.io>
This commit is contained in:
Michael Estes 2025-06-07 17:39:44 -04:00 • committed by Benjamin Cabé
commit bd0efcc948
1 changed files with 10 additions and 8 deletions
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6
drivers/serial/uart_xlnx_uartlite.c
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@ -379,8 +379,10 @@ static DEVICE_API(uart, xlnx_uartlite_driver_api) = {
do { \ do { \
IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \ IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \
DT_INST_IRQ_BY_IDX(n, i, priority), \ DT_INST_IRQ_BY_IDX(n, i, priority), \
xlnx_uartlite_isr, \ xlnx_uartlite_isr, DEVICE_DT_INST_GET(n), \
DEVICE_DT_INST_GET(n), 0); \ COND_CODE_1(DT_INST_IRQ_HAS_CELL_AT_IDX(n, i, flags), \
(DT_INST_IRQ_BY_IDX(n, i, flags)), \
(0))); \
\ \
irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \ irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \
} while (false) } while (false)