diff --git a/arch/riscv32/Kconfig b/arch/riscv32/Kconfig index 0e7003eb2f3..973fb99ae66 100644 --- a/arch/riscv32/Kconfig +++ b/arch/riscv32/Kconfig @@ -21,6 +21,7 @@ config INCLUDE_RESET_VECTOR config RISCV_SOC_CONTEXT_SAVE bool "Enable SOC-based context saving in IRQ handlers" + select RISCV_SOC_OFFSETS help Enable low-level SOC-specific context management, for SOCs with extra state that must be saved when entering an @@ -40,12 +41,6 @@ config RISCV_SOC_CONTEXT_SAVE - SOC_ESF_INIT: structure contents initializer for struct soc_esf state. The last initialized member should not end in a comma. - - GEN_SOC_OFFSET_SYMS(): a macro which expands to - GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls - to ensure offset macros for SOC_ESF_MEMBERS are defined - in offsets.h. The last one should not end in a semicolon. - See gen_offset.h for more details. - The generic architecture IRQ wrapper will also call \_\_soc_save_context and \_\_soc_restore_context routines at ISR entry and exit, respectively. These should typically @@ -59,6 +54,18 @@ config RISCV_SOC_CONTEXT_SAVE The calls obey standard calling conventions; i.e., the state pointer address is in a0, and ra contains the return address. +config RISCV_SOC_OFFSETS + bool "Enable SOC-based offsets" + help + Enabling this option requires that the SoC provide a soc_offsets.h + header which defines the following macros: + + - GEN_SOC_OFFSET_SYMS(): a macro which expands to + GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls + to ensure offset macros for SOC_ESF_MEMBERS are defined + in offsets.h. The last one should not end in a semicolon. + See gen_offset.h for more details. + config RISCV_SOC_INTERRUPT_INIT bool "Enable SOC-based interrupt initialization" help diff --git a/arch/riscv32/core/offsets/offsets.c b/arch/riscv32/core/offsets/offsets.c index 666e8f59599..de76bae7ef9 100644 --- a/arch/riscv32/core/offsets/offsets.c +++ b/arch/riscv32/core/offsets/offsets.c @@ -20,6 +20,9 @@ #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE #include #endif +#ifdef CONFIG_RISCV_SOC_OFFSETS +#include +#endif /* thread_arch_t member offsets */ GEN_OFFSET_SYM(_thread_arch_t, swap_return_value); @@ -64,6 +67,8 @@ GEN_OFFSET_SYM(NANO_ESF, mstatus); #if defined(CONFIG_RISCV_SOC_CONTEXT_SAVE) GEN_OFFSET_SYM(NANO_ESF, soc_context); +#endif +#if defined(CONFIG_RISCV_SOC_OFFSETS) GEN_SOC_OFFSET_SYMS(); #endif diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig index 07dd337061e..8d85e97b2c4 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig +++ b/soc/riscv32/openisa_rv32m1/Kconfig.defconfig @@ -36,6 +36,10 @@ config RISCV_SOC_CONTEXT_SAVE bool default y if SOC_OPENISA_RV32M1_RI5CY +config RISCV_SOC_OFFSETS + bool + default y + config RISCV_SOC_INTERRUPT_INIT bool default y diff --git a/soc/riscv32/openisa_rv32m1/soc_context.h b/soc/riscv32/openisa_rv32m1/soc_context.h index b6ee789d38a..3a7faa19c9d 100644 --- a/soc/riscv32/openisa_rv32m1/soc_context.h +++ b/soc/riscv32/openisa_rv32m1/soc_context.h @@ -31,22 +31,6 @@ 0xdeadbaad, \ 0xdeadbaad -/* - * Ensure offset macros are available in for the above. - * - * Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR, - * for use in assembly. - */ -#define GEN_SOC_OFFSET_SYMS() \ - GEN_OFFSET_SYM(soc_esf_t, lpstart0); \ - GEN_OFFSET_SYM(soc_esf_t, lpend0); \ - GEN_OFFSET_SYM(soc_esf_t, lpcount0); \ - GEN_OFFSET_SYM(soc_esf_t, lpstart1); \ - GEN_OFFSET_SYM(soc_esf_t, lpend1); \ - GEN_OFFSET_SYM(soc_esf_t, lpcount1); \ - GEN_ABSOLUTE_SYM(__EVENT0_INTPTPENDCLEAR, \ - (uint32_t)&EVENT0->INTPTPENDCLEAR) - #endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_ */ diff --git a/soc/riscv32/openisa_rv32m1/soc_irq.S b/soc/riscv32/openisa_rv32m1/soc_irq.S index dd6a72bd1f7..47fef2c99c9 100644 --- a/soc/riscv32/openisa_rv32m1/soc_irq.S +++ b/soc/riscv32/openisa_rv32m1/soc_irq.S @@ -40,7 +40,7 @@ SECTION_FUNC(exception.other, __soc_is_irq) * INTPTPENDCLEAR. */ SECTION_FUNC(exception.other, __soc_handle_irq) - la t0, __EVENT0_INTPTPENDCLEAR + la t0, __EVENT_INTPTPENDCLEAR li t1, 1 sll t1, t1, a0 sw t1, 0x00(t0) diff --git a/soc/riscv32/openisa_rv32m1/soc_offsets.h b/soc/riscv32/openisa_rv32m1/soc_offsets.h new file mode 100644 index 00000000000..7cc08feb569 --- /dev/null +++ b/soc/riscv32/openisa_rv32m1/soc_offsets.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018 Foundries.io Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Extra definitions required for CONFIG_RISCV_SOC_OFFSETS. + */ + +#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ +#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ + +#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY + +/* + * Ensure offset macros are available in . + * + * Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR, + * for use in assembly. + */ +#define GEN_SOC_OFFSET_SYMS() \ + GEN_OFFSET_SYM(soc_esf_t, lpstart0); \ + GEN_OFFSET_SYM(soc_esf_t, lpend0); \ + GEN_OFFSET_SYM(soc_esf_t, lpcount0); \ + GEN_OFFSET_SYM(soc_esf_t, lpstart1); \ + GEN_OFFSET_SYM(soc_esf_t, lpend1); \ + GEN_OFFSET_SYM(soc_esf_t, lpcount1); \ + GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \ + (uint32_t)&EVENT0->INTPTPENDCLEAR) + +#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */ + +#ifdef CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY + +#define GEN_SOC_OFFSET_SYMS() \ + GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \ + (uint32_t)&EVENT1->INTPTPENDCLEAR) + +#endif /* CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY */ + +#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ */