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arch: arm: Rewrite Cortex-R reset vector function.

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This commit addresses the following issues:

1. Add a new Kconfig configuration for specifying Dual-redundant Core
   Lock-step (DCLS) processor topology.

2. Register initialisation is only required when Dual-redundant Core
   Lock-step (DCLS) is implemented in hardware. This initialisation is
   required on DCLS only because the architectural registers are in an
   indeterminate state after reset and therefore the initial register
   state of the two parallel executing cores are not guaranteed to be
   identical, which can lead to DCCM detecting it as a hardware fault.
   A conditional compilation check for this hardware configuration
   using the newly added CONFIG_CPU_HAS_DCLS flag has been added.

3. The existing CPU register initialisation code did not take into
   account the banked registers for every execution mode. The new
   implementation ensures that all architectural registers of every
   mode are initialised.

4. Add VFP register initialisation for when floating-point support is
   enabled and the core is configured in DCLS topology. This
   initialisation sequence is required for the same reason given in
   the first issue.

5. Add provision for platform-specific initialisation on Cortex-R
   using PLATFORM_SPECIFIC_INIT config and z_platform_init function.

6. Remove seemingly pointless and inadequately defined STACK_MARGIN.
   Not only does it violate the 8-byte stack alignment rule, it does
   not provide any form of real stack protection.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2019-10-09 00:52:18 +09:00 • committed by Ioannis Glaropoulos
commit bc8524eb82
3 changed files with 151 additions and 52 deletions
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10
include/arch/arm/aarch32/cortex_r/cpu.h
View file

@ -12,7 +12,7 @@
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_ABT 0x17
#define MODE_UDF 0x1b
#define MODE_UND 0x1b
#define MODE_SYS 0x1f
#define MODE_MASK 0x1f
@ -23,6 +23,14 @@
#define HIVECS (1 << 13)
#define CPACR_NA (0U)
#define CPACR_FA (3U)
#define CPACR_CP10(r) (r << 20)
#define CPACR_CP11(r) (r << 22)
#define FPEXC_EN (1 << 30)
#define RET_FROM_SVC 0
#define RET_FROM_IRQ 1