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drivers: pinctrl: refactor pin control support for imx rt

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Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-04-25 16:30:58 -05:00 • committed by David Leach
commit bc841e1fb7
12 changed files with 144 additions and 120 deletions
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2
drivers/gpio/gpio_mcux_igpio.c
View file

@ -317,7 +317,7 @@ static const struct gpio_driver_api mcux_igpio_driver_api = {
#ifdef CONFIG_PINCTRL
/* These macros will declare an array of pinctrl_soc_pinmux types */
#define PINMUX_INIT(node, prop, idx) MCUX_RT_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
#define MCUX_IGPIO_PIN_DECLARE(n) \
const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \
DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \

2
drivers/pinctrl/CMakeLists.txt
View file

@ -16,7 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)

2
drivers/pinctrl/Kconfig
View file

@ -41,7 +41,7 @@ source "drivers/pinctrl/Kconfig.sam0"
source "drivers/pinctrl/Kconfig.stm32"
source "drivers/pinctrl/Kconfig.kinetis"
source "drivers/pinctrl/Kconfig.xec"
source "drivers/pinctrl/Kconfig.mcux"
source "drivers/pinctrl/Kconfig.imx"
source "drivers/pinctrl/Kconfig.sifive"
source "drivers/pinctrl/Kconfig.lpc_iocon"
source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"

8
drivers/pinctrl/Kconfig.imx Normal file
View file

@ -0,0 +1,8 @@
# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_IMX
bool "Pin controller driver for iMX MCUs"
depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
help
Enable pin controller driver for NXP iMX series MCUs

13
drivers/pinctrl/Kconfig.mcux
View file

@ -1,13 +0,0 @@
# Copyright 2022, NXP
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl
DT_COMPAT_MCUX_RT11XX_PINCTRL := nxp,mcux-rt11xx-pinctrl
config PINCTRL_MCUX_RT
bool "Pin controller driver for MCUX RT1xxx MCUs"
depends on SOC_SERIES_IMX_RT
default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL)) || \
$(dt_compat_enabled,$(DT_COMPAT_MCUX_RT11XX_PINCTRL))
help
Enable pin controller driver for NXP RT1XXX series MCUs

32
drivers/pinctrl/pinctrl_mcux_rt.c → drivers/pinctrl/pinctrl_imx.c
View file

@ -4,12 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <fsl_iomuxc.h>
#include <fsl_gpio.h>
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
@ -23,6 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uint32_t input_daisy = pins[i].pinmux.input_daisy;
uint32_t config_register = pins[i].pinmux.config_register;
uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX)
volatile uint32_t *gpr_register =
(volatile uint32_t *)pins[i].pinmux.gpr_register;
if (gpr_register) {
@ -34,14 +31,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
*gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift);
}
}
IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
input_daisy, config_register,
MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
#endif
*((volatile uint32_t *)mux_register) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags));
if (input_register) {
*((volatile uint32_t *)input_register) =
IOMUXC_SELECT_INPUT_DAISY(input_daisy);
}
if (config_register) {
IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
input_daisy, config_register,
pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
*((volatile uint32_t *)config_register) =
pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT));
}
@ -49,19 +48,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
return 0;
}
static int mcux_pinctrl_init(const struct device *dev)
static int imx_pinctrl_init(const struct device *dev)
{
ARG_UNUSED(dev);
#ifdef CONFIG_SOC_SERIES_IMX_RT
CLOCK_EnableClock(kCLOCK_Iomuxc);
#ifdef CONFIG_SOC_SERIES_IMX_RT10XX
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
CLOCK_EnableClock(kCLOCK_IomuxcGpr);
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr);
#endif
#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */
#elif defined(CONFIG_SOC_MIMX8MQ6)
CLOCK_EnableClock(kCLOCK_Iomux);
#endif /* CONFIG_SOC_SERIES_IMX_RT */
return 0;
}
SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0);
SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0);