diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index 4610c7898a1..70a7928a5cc 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -317,7 +317,7 @@ static const struct gpio_driver_api mcux_igpio_driver_api = { #ifdef CONFIG_PINCTRL /* These macros will declare an array of pinctrl_soc_pinmux types */ -#define PINMUX_INIT(node, prop, idx) MCUX_RT_PINMUX(DT_PROP_BY_IDX(node, prop, idx)), +#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)), #define MCUX_IGPIO_PIN_DECLARE(n) \ const struct pinctrl_soc_pinmux mcux_igpio_pinmux_##n[] = { \ DT_FOREACH_PROP_ELEM(DT_DRV_INST(n), pinmux, PINMUX_INIT) \ diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 502ca666df2..d06c8e6aebc 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -16,7 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c) -zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 4c80e48673b..4c472fa14ed 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -41,7 +41,7 @@ source "drivers/pinctrl/Kconfig.sam0" source "drivers/pinctrl/Kconfig.stm32" source "drivers/pinctrl/Kconfig.kinetis" source "drivers/pinctrl/Kconfig.xec" -source "drivers/pinctrl/Kconfig.mcux" +source "drivers/pinctrl/Kconfig.imx" source "drivers/pinctrl/Kconfig.sifive" source "drivers/pinctrl/Kconfig.lpc_iocon" source "drivers/pinctrl/Kconfig.cc13xx_cc26xx" diff --git a/drivers/pinctrl/Kconfig.imx b/drivers/pinctrl/Kconfig.imx new file mode 100644 index 00000000000..df5afd99a58 --- /dev/null +++ b/drivers/pinctrl/Kconfig.imx @@ -0,0 +1,8 @@ +# Copyright (c) 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_IMX + bool "Pin controller driver for iMX MCUs" + depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC + help + Enable pin controller driver for NXP iMX series MCUs diff --git a/drivers/pinctrl/Kconfig.mcux b/drivers/pinctrl/Kconfig.mcux deleted file mode 100644 index 2ae23a0ab3e..00000000000 --- a/drivers/pinctrl/Kconfig.mcux +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl -DT_COMPAT_MCUX_RT11XX_PINCTRL := nxp,mcux-rt11xx-pinctrl - -config PINCTRL_MCUX_RT - bool "Pin controller driver for MCUX RT1xxx MCUs" - depends on SOC_SERIES_IMX_RT - default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL)) || \ - $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT11XX_PINCTRL)) - help - Enable pin controller driver for NXP RT1XXX series MCUs diff --git a/drivers/pinctrl/pinctrl_mcux_rt.c b/drivers/pinctrl/pinctrl_imx.c similarity index 63% rename from drivers/pinctrl/pinctrl_mcux_rt.c rename to drivers/pinctrl/pinctrl_imx.c index 1bc096df468..d4c9213217c 100644 --- a/drivers/pinctrl/pinctrl_mcux_rt.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -4,12 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl - #include #include -#include -#include int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, @@ -23,6 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t input_daisy = pins[i].pinmux.input_daisy; uint32_t config_register = pins[i].pinmux.config_register; uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; +#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX) volatile uint32_t *gpr_register = (volatile uint32_t *)pins[i].pinmux.gpr_register; if (gpr_register) { @@ -34,14 +31,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, *gpr_register &= ~(0x1 << pins[i].pinmux.gpr_shift); } } - - IOMUXC_SetPinMux(mux_register, mux_mode, input_register, - input_daisy, config_register, - MCUX_RT_INPUT_ENABLE(pin_ctrl_flags)); +#endif + *((volatile uint32_t *)mux_register) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | + IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)); + if (input_register) { + *((volatile uint32_t *)input_register) = + IOMUXC_SELECT_INPUT_DAISY(input_daisy); + } if (config_register) { - IOMUXC_SetPinConfig(mux_register, mux_mode, input_register, - input_daisy, config_register, - pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT))); + *((volatile uint32_t *)config_register) = + pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)); } @@ -49,19 +48,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, return 0; } -static int mcux_pinctrl_init(const struct device *dev) +static int imx_pinctrl_init(const struct device *dev) { ARG_UNUSED(dev); - +#ifdef CONFIG_SOC_SERIES_IMX_RT CLOCK_EnableClock(kCLOCK_Iomuxc); #ifdef CONFIG_SOC_SERIES_IMX_RT10XX CLOCK_EnableClock(kCLOCK_IomuxcSnvs); CLOCK_EnableClock(kCLOCK_IomuxcGpr); #elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); -#endif +#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */ +#elif defined(CONFIG_SOC_MIMX8MQ6) + CLOCK_EnableClock(kCLOCK_Iomux); +#endif /* CONFIG_SOC_SERIES_IMX_RT */ return 0; } -SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0); +SYS_INIT(imx_pinctrl_init, PRE_KERNEL_1, 0); diff --git a/modules/Kconfig.imx b/modules/Kconfig.imx index 6aacd9b72b7..5b387f1e9a5 100644 --- a/modules/Kconfig.imx +++ b/modules/Kconfig.imx @@ -25,4 +25,9 @@ config HAS_IMX_EPIT help Set if the EPIT module is present in the SoC. +config HAS_IMX_IOMUXC + bool + help + Set if the IOMUXC module is present in the SoC. + endif # HAS_IMX_HAL diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index e085ff76d86..47a24daf455 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -116,6 +116,11 @@ config HAS_MCUX_IGPIO help Set if the iMX GPIO (IGPIO) module is present in the SoC. +config HAS_MCUX_IOMUXC + bool + help + Set if the iMX I/O mux controller (IOMUXC) is present in the SoC. + config HAS_MCUX_LPI2C bool help diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series index fe9db67f092..71c298c293b 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series +++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series @@ -32,6 +32,10 @@ config GPIO_MCUX_IGPIO default y if HAS_MCUX_IGPIO depends on GPIO +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + config ENTROPY_MCUX_TRNG default y if HAS_MCUX_TRNG depends on ENTROPY_GENERATOR diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index d9a7741f711..4a01f72db8f 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -28,6 +28,7 @@ config SOC_MIMXRT1011 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1015 bool "SOC_MIMXRT1015" @@ -51,6 +52,7 @@ config SOC_MIMXRT1015 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1021 bool "SOC_MIMXRT1021" @@ -80,6 +82,7 @@ config SOC_MIMXRT1021 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1024 bool "SOC_MIMXRT1024" @@ -109,6 +112,7 @@ config SOC_MIMXRT1024 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1051 bool "SOC_MIMXRT1051" @@ -138,6 +142,7 @@ config SOC_MIMXRT1051 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1052 bool "SOC_MIMXRT1052" @@ -171,6 +176,7 @@ config SOC_MIMXRT1052 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1061 bool "SOC_MIMXRT1061" @@ -200,6 +206,7 @@ config SOC_MIMXRT1061 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1062 bool "SOC_MIMXRT1062" @@ -235,6 +242,7 @@ config SOC_MIMXRT1062 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1064 bool "SOC_MIMXRT1064" @@ -271,6 +279,7 @@ config SOC_MIMXRT1064 select HAS_MCUX_GPC select HAS_MCUX_DCDC select HAS_MCUX_PMU + select HAS_MCUX_IOMUXC config SOC_MIMXRT1176_CM7 bool "SOC_MIMXRT1176_CM7" @@ -309,6 +318,7 @@ config SOC_MIMXRT1176_CM7 select HAS_MCUX_I2S select HAS_MCUX_USB_EHCI select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC config SOC_MIMXRT1176_CM4 bool "SOC_MIMXRT1176_CM4" @@ -336,6 +346,7 @@ config SOC_MIMXRT1176_CM4 select HAS_MCUX_GPC select HAS_MCUX_I2S select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC config SOC_MIMXRT1166_CM7 bool "SOC_MIMXRT1166_CM7" @@ -371,6 +382,7 @@ config SOC_MIMXRT1166_CM7 select HAS_MCUX_GPC select HAS_MCUX_USB_EHCI select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC config SOC_MIMXRT1166_CM4 @@ -398,6 +410,7 @@ config SOC_MIMXRT1166_CM4 select HAS_MCUX_ENET select HAS_MCUX_GPC select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC endchoice diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h b/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h index 6b28394dadf..f95abbccb58 100644 --- a/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h +++ b/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h @@ -15,32 +15,32 @@ extern "C" { #endif -#define MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT -#define MCUX_RT_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT -#define MCUX_RT_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT -#define MCUX_RT_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT -#define MCUX_RT_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT -#define MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT -#define MCUX_RT_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT -#define MCUX_RT_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT -#define MCUX_RT_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT -#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ -#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1) +#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT +#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT +#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT +#define MCUX_IMX_BIAS_BUS_HOLD_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT +#define MCUX_IMX_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT +#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT +#define MCUX_IMX_SPEED_SHIFT IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT +#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT +#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT +#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) -#define Z_PINCTRL_MCUX_RT_PINCFG_INIT(node_id) \ - ((DT_PROP(node_id, input_schmitt_enable) << MCUX_RT_INPUT_SCHMITT_ENABLE_SHIFT) | \ +#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ IF_ENABLED(DT_PROP(node_id, bias_pull_up), (DT_ENUM_IDX(node_id, bias_pull_up_value) \ - << MCUX_RT_BIAS_PULL_UP_SHIFT) |) \ + << MCUX_IMX_BIAS_PULL_UP_SHIFT) |) \ IF_ENABLED(DT_PROP(node_id, bias_pull_down), (DT_ENUM_IDX(node_id, bias_pull_down_value)\ - << MCUX_RT_BIAS_PULL_DOWN_SHIFT) |) \ - ((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \ - << MCUX_RT_BIAS_BUS_HOLD_SHIFT) | \ - ((!DT_PROP(node_id, bias_disable)) << MCUX_RT_PULL_ENABLE_SHIFT) | \ - (DT_PROP(node_id, drive_open_drain) << MCUX_RT_DRIVE_OPEN_DRAIN_SHIFT) | \ - (DT_ENUM_IDX(node_id, nxp_speed) << MCUX_RT_SPEED_SHIFT) | \ - (DT_ENUM_IDX(node_id, drive_strength) << MCUX_RT_DRIVE_STRENGTH_SHIFT) | \ - (DT_ENUM_IDX(node_id, slew_rate) << MCUX_RT_SLEW_RATE_SHIFT) | \ - (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT)) + << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |) \ + ((DT_PROP(node_id, bias_pull_down) | DT_PROP(node_id, bias_pull_up)) \ + << MCUX_IMX_BIAS_BUS_HOLD_SHIFT) | \ + ((!DT_PROP(node_id, bias_disable)) << MCUX_IMX_PULL_ENABLE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ + (DT_ENUM_IDX(node_id, nxp_speed) << MCUX_IMX_SPEED_SHIFT) | \ + (DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ + (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) /* This struct must be present. It is used by the mcux gpio driver */ @@ -63,7 +63,7 @@ struct pinctrl_soc_pin { typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; /* This definition must be present. It is used by the mcux gpio driver */ -#define MCUX_RT_PINMUX(node_id) \ +#define MCUX_IMX_PINMUX(node_id) \ { \ .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ @@ -79,12 +79,12 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; } #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ - MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) -#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ - { \ - .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ - .pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PINCFG_INIT(group_id), \ +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ }, diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h b/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h index c6e2441969c..04d652635c3 100644 --- a/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h +++ b/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h @@ -15,19 +15,19 @@ extern "C" { #endif -#define MCUX_RT_ODE_SHIFT 4 -#define MCUX_RT_PUS_SHIFT 3 -#define MCUX_RT_PUE_SHIFT 2 -#define MCUX_RT_DSE_SHIFT 1 -#define MCUX_RT_SRE_SHIFT 0 -#define MCUX_RT_PULL_SHIFT 2 -#define MCUX_RT_PULL_PULLDOWN 0x2 -#define MCUX_RT_PULL_PULLUP 0x1 -#define MCUX_RT_PDRV_SHIFT 1 -#define MCUX_RT_LPSR_ODE_SHIFT 5 -#define MCUX_RT_SNVS_ODE_SHIFT 6 -#define MCUX_RT_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ -#define MCUX_RT_INPUT_ENABLE(x) ((x >> MCUX_RT_INPUT_ENABLE_SHIFT) & 0x1) +#define MCUX_IMX_ODE_SHIFT 4 +#define MCUX_IMX_PUS_SHIFT 3 +#define MCUX_IMX_PUE_SHIFT 2 +#define MCUX_IMX_DSE_SHIFT 1 +#define MCUX_IMX_SRE_SHIFT 0 +#define MCUX_IMX_PULL_SHIFT 2 +#define MCUX_IMX_PULL_PULLDOWN 0x2 +#define MCUX_IMX_PULL_PULLUP 0x1 +#define MCUX_IMX_PDRV_SHIFT 1 +#define MCUX_IMX_LPSR_ODE_SHIFT 5 +#define MCUX_IMX_SNVS_ODE_SHIFT 6 +#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) /* @@ -39,55 +39,55 @@ extern "C" { * pue_pus_snvs: in SNVS domain, shifted ode field */ -#define MCUX_RT_PUS_PUE 0 -#define MCUX_RT_PDRV_PULL 1 -#define MCUX_RT_LPSR 2 -#define MCUX_RT_SNVS 3 +#define MCUX_IMX_PUS_PUE 0 +#define MCUX_IMX_PDRV_PULL 1 +#define MCUX_IMX_LPSR 2 +#define MCUX_IMX_SNVS 3 /* - * Macro for MCUX_RT_PULL_NOPULL, which needs to set field to 0x3 if two + * Macro for MCUX_IMX_PULL_NOPULL, which needs to set field to 0x3 if two * properties are false */ -#define MCUX_RT_NOPULL(node_id) \ +#define MCUX_IMX_NOPULL(node_id) \ ((0x2 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 1)) |\ (0x1 & ((!DT_PROP(node_id, bias_pull_down) && !DT_PROP(node_id, bias_pull_up)) << 0))) \ -#define Z_PINCTRL_MCUX_RT_PDRV(node_id) \ +#define Z_PINCTRL_MCUX_IMX_PDRV(node_id) \ IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ - (MCUX_RT_PULL_PULLDOWN << MCUX_RT_PULL_SHIFT) |) \ + (MCUX_IMX_PULL_PULLDOWN << MCUX_IMX_PULL_SHIFT) |) \ IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ - (MCUX_RT_PULL_PULLUP << MCUX_RT_PULL_SHIFT) |) \ - (MCUX_RT_NOPULL(node_id) << MCUX_RT_PULL_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_PDRV_SHIFT) | \ - (DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \ - (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT) + (MCUX_IMX_PULL_PULLUP << MCUX_IMX_PULL_SHIFT) |) \ + (MCUX_IMX_NOPULL(node_id) << MCUX_IMX_PULL_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_PDRV_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) -#define Z_PINCTRL_MCUX_RT_PUE_PUS(node_id) \ - (DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \ +#define Z_PINCTRL_MCUX_IMX_PUE_PUS(node_id) \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \ ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \ - << MCUX_RT_PUE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \ - (DT_PROP(node_id, drive_open_drain) << MCUX_RT_ODE_SHIFT) | \ - (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT) + << MCUX_IMX_PUE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_ODE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) -#define Z_PINCTRL_MCUX_RT_LPSR(node_id) \ - (DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \ +#define Z_PINCTRL_MCUX_IMX_LPSR(node_id) \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \ ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \ - << MCUX_RT_PUE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \ - (DT_PROP(node_id, drive_open_drain) << MCUX_RT_LPSR_ODE_SHIFT) | \ - (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT) + << MCUX_IMX_PUE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_LPSR_ODE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) -#define Z_PINCTRL_MCUX_RT_SNVS(node_id) \ - (DT_PROP(node_id, bias_pull_up) << MCUX_RT_PUS_SHIFT) | \ +#define Z_PINCTRL_MCUX_IMX_SNVS(node_id) \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_PUS_SHIFT) | \ ((DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down)) \ - << MCUX_RT_PUE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_RT_DSE_SHIFT) | \ - (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_RT_SRE_SHIFT) | \ - (DT_PROP(node_id, drive_open_drain) << MCUX_RT_SNVS_ODE_SHIFT) | \ - (DT_PROP(node_id, input_enable) << MCUX_RT_INPUT_ENABLE_SHIFT) + << MCUX_IMX_PUE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, drive_strength, 0) << MCUX_IMX_DSE_SHIFT) | \ + (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << MCUX_IMX_SRE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_SNVS_ODE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT) /* This struct must be present. It is used by the mcux gpio driver */ struct pinctrl_soc_pinmux { @@ -113,7 +113,7 @@ struct pinctrl_soc_pin { typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; /* This definition must be present. It is used by the mcux gpio driver */ -#define MCUX_RT_PINMUX(node_id) \ +#define MCUX_IMX_PINMUX(node_id) \ { \ .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ @@ -133,19 +133,19 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; } #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ - MCUX_RT_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) -#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ - { \ - .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ -IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \ - (.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PUE_PUS(group_id),)) \ -IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \ - (.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_PDRV(group_id),)) \ -IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \ - (.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_LPSR(group_id),)) \ -IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \ - (.pin_ctrl_flags = Z_PINCTRL_MCUX_RT_SNVS(group_id),)) \ +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ +IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pue), \ + (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PUE_PUS(group_id),)) \ +IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_pdrv), \ + (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PDRV(group_id),)) \ +IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_lpsr), \ + (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_LPSR(group_id),)) \ +IF_ENABLED(DT_PROP(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx), pin_snvs), \ + (.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_SNVS(group_id),)) \ },