drivers: pwm: nrf_sw: support generating PWM based on RTC
So far nRF's TIMER was used for generating PWM signal. Add support for generating PWM based on RTC, which is sourced by 32KHz low frequency crystal. This allows to use low frequency PWM with much lower power consumption, because high frequency clock path can be disabled. Don't support RTC clock prescaler, because maximum 512s period covers most use cases. This allows to adjust pulse and period cycles to the fact that CLEAR task event is generated always one LFCLK cycle after period COMPARE value is reached. Also update hal_nordic revision, as it contains updated check for PPI channels conflict when RTC is used to generate PWM. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This commit is contained in:
Marcin Niestroj
Carles Cufí
parent
0d58960abb
commit
bc5a6164c9
4 changed files with 179 additions and 59 deletions
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@ -21,13 +21,27 @@ BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, timer_instance) !=
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"Please define either the timer-instance or generator property, but not both");
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#if DT_INST_NODE_HAS_PROP(0, timer_instance)
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#define USE_RTC 0
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#define GENERATOR_ADDR _CONCAT(NRF_TIMER, DT_INST_PROP(0, timer_instance))
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#define GENERATOR_CC_NUM \
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_CONCAT(_CONCAT(TIMER, DT_INST_PROP(0, timer_instance)), _CC_NUM)
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#else /* DT_INST_NODE_HAS_PROP(0, timer_instance) */
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#define GENERATOR_NODE DT_PHANDLE(DT_DRV_INST(0), generator)
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#define GENERATOR_ADDR ((NRF_TIMER_Type *) DT_REG_ADDR(GENERATOR_NODE))
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#define GENERATOR_CC_NUM DT_PROP(GENERATOR_NODE, cc_num)
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#if DT_NODE_HAS_COMPAT(GENERATOR_NODE, nordic_nrf_rtc)
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#define USE_RTC 1
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#define GENERATOR_ADDR ((NRF_RTC_Type *) DT_REG_ADDR(GENERATOR_NODE))
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BUILD_ASSERT(DT_INST_PROP(0, clock_prescaler) == 0,
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"Only clock-prescaler = <0> is supported when used with RTC");
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#else
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#define USE_RTC 0
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#define GENERATOR_ADDR ((NRF_TIMER_Type *) DT_REG_ADDR(GENERATOR_NODE))
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#endif
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#endif /* DT_INST_NODE_HAS_PROP(0, timer_instance) */
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/* One compare channel is needed to set the PWM period, hence +1. */
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@ -37,7 +51,10 @@ BUILD_ASSERT(DT_INST_NODE_HAS_PROP(0, timer_instance) !=
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#define PWM_0_MAP_SIZE DT_INST_PROP(0, channel_count)
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struct pwm_config {
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NRF_TIMER_Type *timer;
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union {
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NRF_RTC_Type *rtc;
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NRF_TIMER_Type *timer;
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};
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uint8_t gpiote_base;
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uint8_t ppi_base;
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uint8_t map_size;
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@ -54,6 +71,24 @@ struct pwm_data {
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struct chan_map map[PWM_0_MAP_SIZE];
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};
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static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config)
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{
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#if USE_RTC
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return config->rtc;
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#else
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return NULL;
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#endif
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}
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static inline NRF_TIMER_Type *pwm_config_timer(const struct pwm_config *config)
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{
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#if !USE_RTC
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return config->timer;
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#else
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return NULL;
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#endif
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}
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static uint32_t pwm_period_check(struct pwm_data *data, uint8_t map_size,
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uint32_t pwm, uint32_t period_cycles,
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uint32_t pulse_cycles)
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@ -104,17 +139,15 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_config *config;
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NRF_TIMER_Type *timer;
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struct pwm_data *data;
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const struct pwm_config *config = dev->config;
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NRF_TIMER_Type *timer = pwm_config_timer(config);
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NRF_RTC_Type *rtc = pwm_config_rtc(config);
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struct pwm_data *data = dev->data;
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uint8_t ppi_index;
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uint32_t ppi_mask;
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uint8_t channel;
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uint32_t ret;
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config = (const struct pwm_config *)dev->config;
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timer = config->timer;
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data = dev->data;
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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@ -130,13 +163,21 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
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return ret;
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}
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/* TODO: if the assigned NRF_TIMER supports higher bit resolution,
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* use that info in config struct.
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*/
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if (period_cycles > BIT_MASK(16)) {
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LOG_ERR("Too long period (%u), adjust pwm prescaler!",
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period_cycles);
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return -EINVAL;
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if (USE_RTC) {
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/* pulse_cycles - 1 is written to 24-bit CC */
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if (period_cycles > BIT_MASK(24) + 1) {
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LOG_ERR("Too long period (%u)!", period_cycles);
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return -EINVAL;
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}
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} else {
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/* TODO: if the assigned NRF_TIMER supports higher bit
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* resolution, use that info in config struct.
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*/
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if (period_cycles > UINT16_MAX) {
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LOG_ERR("Too long period (%u), adjust pwm prescaler!",
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period_cycles);
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return -EINVAL;
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}
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}
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/* map pwm pin to GPIOTE config/channel */
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@ -153,8 +194,15 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
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NRF_GPIOTE->CONFIG[config->gpiote_base + channel] = 0;
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/* clear PPI used */
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ppi_index = config->ppi_base + (channel << 1);
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NRF_PPI->CHENCLR = BIT(ppi_index) | BIT(ppi_index + 1);
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if (USE_RTC) {
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ppi_index = config->ppi_base + (channel * 3);
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ppi_mask = BIT(ppi_index) | BIT(ppi_index + 1) |
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BIT(ppi_index + 2);
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} else {
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ppi_index = config->ppi_base + (channel * 2);
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ppi_mask = BIT(ppi_index) | BIT(ppi_index + 1);
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}
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NRF_PPI->CHENCLR = ppi_mask;
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/* configure GPIO pin as output */
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nrf_gpio_cfg_output(pwm);
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@ -173,32 +221,64 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
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nrf_gpio_pin_clear(pwm);
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}
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/* configure TIMER */
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timer->EVENTS_COMPARE[channel] = 0;
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timer->EVENTS_COMPARE[config->map_size] = 0;
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/* configure RTC / TIMER */
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if (USE_RTC) {
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rtc->EVENTS_COMPARE[channel] = 0;
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rtc->EVENTS_COMPARE[config->map_size] = 0;
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timer->CC[channel] = pulse_cycles;
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timer->CC[config->map_size] = period_cycles;
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timer->TASKS_CLEAR = 1;
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/*
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* '- 1' adjusts pulse and period cycles to the fact that CLEAR
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* task event is generated always one LFCLK cycle after period
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* COMPARE value is reached.
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*/
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rtc->CC[channel] = pulse_cycles - 1;
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rtc->CC[config->map_size] = period_cycles - 1;
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rtc->TASKS_CLEAR = 1;
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} else {
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timer->EVENTS_COMPARE[channel] = 0;
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timer->EVENTS_COMPARE[config->map_size] = 0;
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timer->CC[channel] = pulse_cycles;
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timer->CC[config->map_size] = period_cycles;
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timer->TASKS_CLEAR = 1;
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}
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/* configure GPIOTE, toggle with initialise output high */
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NRF_GPIOTE->CONFIG[config->gpiote_base + channel] = 0x00130003 |
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(pwm << 8);
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/* setup PPI */
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NRF_PPI->CH[ppi_index].EEP = (uint32_t)
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&(timer->EVENTS_COMPARE[channel]);
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NRF_PPI->CH[ppi_index].TEP = (uint32_t)
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&(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CH[ppi_index + 1].EEP = (uint32_t)
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&(timer->EVENTS_COMPARE[
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config->map_size]);
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NRF_PPI->CH[ppi_index + 1].TEP = (uint32_t)
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&(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CHENSET = BIT(ppi_index) | BIT(ppi_index + 1);
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if (USE_RTC) {
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NRF_PPI->CH[ppi_index].EEP =
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(uint32_t) &(rtc->EVENTS_COMPARE[channel]);
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NRF_PPI->CH[ppi_index].TEP =
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(uint32_t) &(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CH[ppi_index + 1].EEP =
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(uint32_t) &(rtc->EVENTS_COMPARE[config->map_size]);
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NRF_PPI->CH[ppi_index + 1].TEP =
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(uint32_t) &(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CH[ppi_index + 2].EEP =
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(uint32_t) &(rtc->EVENTS_COMPARE[config->map_size]);
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NRF_PPI->CH[ppi_index + 2].TEP =
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(uint32_t) &(rtc->TASKS_CLEAR);
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} else {
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NRF_PPI->CH[ppi_index].EEP =
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(uint32_t) &(timer->EVENTS_COMPARE[channel]);
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NRF_PPI->CH[ppi_index].TEP =
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(uint32_t) &(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CH[ppi_index + 1].EEP =
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(uint32_t) &(timer->EVENTS_COMPARE[config->map_size]);
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NRF_PPI->CH[ppi_index + 1].TEP =
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(uint32_t) &(NRF_GPIOTE->TASKS_OUT[channel]);
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}
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NRF_PPI->CHENSET = ppi_mask;
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/* start timer, hence PWM */
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timer->TASKS_START = 1;
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if (USE_RTC) {
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rtc->TASKS_START = 1;
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} else {
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timer->TASKS_START = 1;
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}
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/* store the pwm/pin and its param */
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data->period_cycles = period_cycles;
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@ -221,7 +301,11 @@ pin_set_pwm_off:
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if (!pwm_active) {
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/* No active PWM, stop timer */
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timer->TASKS_STOP = 1;
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if (USE_RTC) {
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rtc->TASKS_STOP = 1;
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} else {
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timer->TASKS_STOP = 1;
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}
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}
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return 0;
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@ -231,12 +315,21 @@ static int pwm_nrf5_sw_get_cycles_per_sec(const struct device *dev,
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uint32_t pwm,
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uint64_t *cycles)
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{
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const struct pwm_config *config;
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const struct pwm_config *config = dev->config;
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config = (const struct pwm_config *)dev->config;
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/* HF timer frequency is derived from 16MHz source with a prescaler */
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*cycles = 16000000UL / BIT(config->prescaler);
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if (USE_RTC) {
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/*
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* RTC frequency is derived from 32768Hz source without any
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* prescaler
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*/
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*cycles = 32768UL;
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} else {
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/*
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* HF timer frequency is derived from 16MHz source with a
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* prescaler
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*/
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*cycles = 16000000UL / BIT(config->prescaler);
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}
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return 0;
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}
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@ -248,27 +341,41 @@ static const struct pwm_driver_api pwm_nrf5_sw_drv_api_funcs = {
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static int pwm_nrf5_sw_init(const struct device *dev)
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{
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const struct pwm_config *config;
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NRF_TIMER_Type *timer;
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const struct pwm_config *config = dev->config;
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NRF_TIMER_Type *timer = pwm_config_timer(config);
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NRF_RTC_Type *rtc = pwm_config_rtc(config);
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config = (const struct pwm_config *)dev->config;
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timer = config->timer;
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if (USE_RTC) {
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/* setup RTC */
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rtc->PRESCALER = 0;
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/* setup HF timer */
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timer->MODE = TIMER_MODE_MODE_Timer;
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timer->PRESCALER = config->prescaler;
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timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
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/*
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* TODO: set EVTEN to map_size if not 3, i.e. if RTC supports
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* less than 4 compares, then less channels can be supported.
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*/
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rtc->EVTENSET = (RTC_EVTENSET_COMPARE0_Msk |
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RTC_EVTENSET_COMPARE1_Msk |
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RTC_EVTENSET_COMPARE2_Msk |
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RTC_EVTENSET_COMPARE3_Msk);
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} else {
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/* setup HF timer */
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timer->MODE = TIMER_MODE_MODE_Timer;
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timer->PRESCALER = config->prescaler;
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timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
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/* TODO: set shorts according to map_size if not 3, i.e. if NRF_TIMER
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* supports more than 4 compares, then more channels can be supported.
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*/
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timer->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk;
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/*
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* TODO: set shorts according to map_size if not 3, i.e. if
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* NRF_TIMER supports more than 4 compares, then more channels
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* can be supported.
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*/
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timer->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk;
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}
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return 0;
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}
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static const struct pwm_config pwm_nrf5_sw_0_config = {
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.timer = GENERATOR_ADDR,
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COND_CODE_1(USE_RTC, (.rtc), (.timer)) = GENERATOR_ADDR,
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.ppi_base = DT_INST_PROP(0, ppi_base),
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.gpiote_base = DT_INST_PROP(0, gpiote_base),
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.map_size = PWM_0_MAP_SIZE,
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