drivers: dmic: APIs for digital microphones
API definition for Digital Microphone Controller(s). Intended for SoCs with Pulse Digital Modulation controllers configured for microphone array applications Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
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Sathish Kuttan
Anas Nashif
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276
include/audio/dmic.h
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276
include/audio/dmic.h
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/*
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* Copyright (c) 2018, Intel Corporation
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*
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* Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
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* Sathish Kuttan <sathish.k.kuttan@intel.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __AUDIO_DMIC_H__
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#define __AUDIO_DMIC_H__
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#include <kernel.h>
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#include <device.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* DMIC driver states
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*/
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enum dmic_state {
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DMIC_STATE_UNINIT, /* Uninitialized */
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DMIC_STATE_INITIALIZED, /* Initialized */
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DMIC_STATE_CONFIGURED, /* Configured */
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DMIC_STATE_ACTIVE, /* Active */
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DMIC_STATE_PAUSED, /* Paused */
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};
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/**
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* DMIC driver trigger commands
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*/
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enum dmic_trigger {
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DMIC_TRIGGER_STOP, /* stop stream */
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DMIC_TRIGGER_START, /* start stream */
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DMIC_TRIGGER_PAUSE, /* pause the stream */
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DMIC_TRIGGER_RELEASE, /* release paused stream */
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DMIC_TRIGGER_RESET, /* reset */
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};
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/**
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* PDM Channels LEFT / RIGHT
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*/
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enum pdm_lr {
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PDM_CHAN_LEFT,
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PDM_CHAN_RIGHT,
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};
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/**
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* PDM Input/Output signal configuration
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*/
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struct pdm_io_cfg {
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/* parameters global to all PDM controllers */
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/* minimum clock frequency supported by the mic */
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u32_t min_pdm_clk_freq;
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/* maximum clock frequency supported by the mic */
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u32_t max_pdm_clk_freq;
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/* minimum duty cycle in % supported by the mic */
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u8_t min_pdm_clk_dc;
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/* maximum duty cycle in % supported by the mic */
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u8_t max_pdm_clk_dc;
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/* parameters unique to each PDM controller */
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/* Bit mask to optionally invert PDM clock */
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u8_t pdm_clk_pol;
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/* Bit mask to optionally invert mic data */
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u8_t pdm_data_pol;
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/* Collection of clock skew values for each PDM port */
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u32_t pdm_clk_skew;
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};
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/**
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* Configuration of the PCM streams to be output by the PDM hardware
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*/
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struct pcm_stream_cfg {
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/*
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* if either rate or width is set to 0 for a stream,
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* the stream would be disabled
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*/
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/* PCM sample rate of stream */
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u32_t pcm_rate;
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/* PCM sample width of stream */
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u8_t pcm_width;
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/* PCM sample block size per transfer */
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u16_t block_size;
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/* SLAB for DMIC driver to allocate buffers for stream */
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struct k_mem_slab *mem_slab;
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};
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/**
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* Mapping/ordering of the PDM channels to logical PCM output channel
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*/
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struct pdm_chan_cfg {
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/*
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* mapping of PDM controller and mic channel to logical channel
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* since each controller can have 2 audio channels (stereo),
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* there can be total of 8x2=16 channels.
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* The actual number of channels shall be described in
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* pcm_stream_cfg.num_chan.
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* if 2 streams are enabled, the channel order will be the same for
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* both streams
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* Each channel is described as a 4 bit number, the least significant
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* bit indicates LEFT/RIGHT selection of the PDM controller.
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* The most significant 3 bits indicate the PDM controller number.
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* bits 0-3 are for channel 0, bit 0 indicates LEFT or RIGHT
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* bits 4-7 are for channel 1, bit 4 indicates LEFT or RIGHT
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* and so on.
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* CONSTRAINT: The LEFT and RIGHT channels of EACH PDM controller needs
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* to be adjacent to each other.
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*/
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/* Requested channel map */
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u32_t req_chan_map_lo; /* Channels 0 to 7 */
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u32_t req_chan_map_hi; /* Channels 8 to 15 */
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/* Actual channel map that the driver could configure */
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u32_t act_chan_map_lo; /* Channels 0 to 7 */
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u32_t act_chan_map_hi; /* Channels 8 to 15 */
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/* requested number of channels */
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u8_t req_num_chan;
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/* Actual number of channels that the driver could configure */
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u8_t act_num_chan;
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/* requested number of streams for each channel */
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u8_t req_num_streams;
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/* Actual number of streams that the driver could configure */
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u8_t act_num_streams;
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};
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/**
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* Input configuration structure for the DMIC configuration API
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*/
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struct dmic_cfg {
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struct pdm_io_cfg io;
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/*
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* Array of pcm_stream_cfg for application to provide
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* configuration for each stream
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*/
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struct pcm_stream_cfg *streams;
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struct pdm_chan_cfg channel;
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};
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/**
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* Function pointers for the DMIC driver operations
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*/
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struct _dmic_ops {
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int (*configure)(struct device *dev, struct dmic_cfg *config);
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int (*trigger)(struct device *dev, enum dmic_trigger cmd);
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int (*read)(struct device *dev, u8_t stream, void **buffer,
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size_t *size, s32_t timeout);
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};
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/**
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* Build the channel map to populate struct pdm_chan_cfg
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*
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* Returns the map of PDM controller and LEFT/RIGHT channel shifted to
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* the bit position corresponding to the input logical channel value
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*
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* @param channel The logical channel number
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* @param pdm The PDM hardware controller number
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* @param lr LEFT/RIGHT channel within the chosen PDM hardware controller
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*
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* @return Bit-map containing the PDM and L/R channel information
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*/
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static inline u32_t dmic_build_channel_map(u8_t channel, u8_t pdm,
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enum pdm_lr lr)
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{
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return ((((pdm & BIT_MASK(3)) << 1) | lr) <<
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((channel & BIT_MASK(3)) * 4));
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}
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/**
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* Helper function to parse the channel map in pdm_chan_cfg
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*
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* Returns the PDM controller and LEFT/RIGHT channel corresponding to
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* the channel map and the logical channel provided as input
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*
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* @param channel_map_lo Lower order/significant bits of the channel map
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* @param channel_map_hi Higher order/significant bits of the channel map
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* @param channel The logical channel number
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* @param pdm Pointer to the PDM hardware controller number
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* @param lr Pointer to the LEFT/RIGHT channel within the PDM controller
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*
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* @return none
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*/
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static inline void dmic_parse_channel_map(u32_t channel_map_lo,
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u32_t channel_map_hi, u8_t channel, u8_t *pdm, enum pdm_lr *lr)
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{
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u32_t channel_map;
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channel_map = (channel < 8) ? channel_map_lo : channel_map_hi;
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channel_map >>= ((channel & BIT_MASK(3)) * 4);
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*pdm = (channel >> 1) & BIT_MASK(3);
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*lr = channel & BIT(0);
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}
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/**
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* Build a bit map of clock skew values for each PDM channel
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*
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* Returns the bit-map of clock skew value shifted to the bit position
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* corresponding to the input PDM controller value
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*
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* @param pdm The PDM hardware controller number
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* @param skew The skew to apply for the clock output from the PDM controller
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*
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* @return Bit-map containing the clock skew information
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*/
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static inline u32_t dmic_build_clk_skew_map(u8_t pdm, u8_t skew)
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{
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return ((skew & BIT_MASK(4)) << ((pdm & BIT_MASK(3)) * 4));
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}
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/**
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* Configure the DMIC driver and controller(s)
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*
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* Configures the DMIC driver device according to the number of channels,
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* channel mapping, PDM I/O configuration, PCM stream configuration, etc.
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*
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* @param dev Pointer to the device structure for DMIC driver instance
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* @param cfg Pointer to the structure containing the DMIC configuration
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*
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* @return 0 on success, a negative error code on failure
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*/
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static inline int dmic_configure(struct device *dev, struct dmic_cfg *cfg)
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{
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const struct _dmic_ops *api = dev->driver_api;
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return api->configure(dev, cfg);
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}
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/**
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* Send a command to the DMIC driver
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*
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* Sends a command to the driver to perform a specific action
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*
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* @param dev Pointer to the device structure for DMIC driver instance
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* @param cmd The command to be sent to the driver instance
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*
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* @return 0 on success, a negative error code on failure
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*/
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static inline int dmic_trigger(struct device *dev, enum dmic_trigger cmd)
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{
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const struct _dmic_ops *api = dev->driver_api;
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return api->trigger(dev, cmd);
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}
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/**
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* Read received decimated PCM data stream
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*
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* Optionally waits for audio to be received and provides the received
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* audio buffer from the requested stream
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*
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* @param dev Pointer to the device structure for DMIC driver instance
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* @param stream Stream identifier
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* @param buffer Pointer to the received buffer address
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* @param size Pointer to the received buffer size
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* @param timeout Timeout value to wait in case audio is not yet received
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*
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* @return 0 on success, a negative error code on failure
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*/
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static inline int dmic_read(struct device *dev, u8_t stream, void **buffer,
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size_t *size, s32_t timeout)
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{
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const struct _dmic_ops *api = dev->driver_api;
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return api->read(dev, stream, buffer, size, timeout);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AUDIO_DMIC_H__ */
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