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dts: arm: provider support for the stm32l0

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Add necessary DTS files for stm32l0x and stm32l0x72

Signed-off-by: Endre Karlson <endre.karlson@gmail.com>
This commit is contained in:
Endre Karlson 2018-02-02 17:13:05 +01:00 • committed by Kumar Gala
commit bbb4b402b2
4 changed files with 122 additions and 0 deletions
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3
dts/arm/st/mem.h
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@ -79,6 +79,9 @@
#define DT_FLASH_SIZE __SIZE_K(2048) #define DT_FLASH_SIZE __SIZE_K(2048)
#define DT_SRAM_SIZE __SIZE_K(384) #define DT_SRAM_SIZE __SIZE_K(384)
#define DT_CCM_SIZE __SIZE_K(64) #define DT_CCM_SIZE __SIZE_K(64)
#elif defined(CONFIG_SOC_STM32L072XZ)
#define DT_FLASH_SIZE __SIZE_K(192)
#define DT_SRAM_SIZE __SIZE_K(20)
#elif defined(CONFIG_SOC_STM32L475XG) #elif defined(CONFIG_SOC_STM32L475XG)
#define DT_FLASH_SIZE __SIZE_K(1024) #define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(96) #define DT_SRAM_SIZE __SIZE_K(96)

26
dts/arm/st/stm32l0-pinctrl.dtsi Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/stm32-pinctrl.h>
/ {
soc {
pinctrl: pin-controller {
usart1_pins_a: usart1@0 {
rx_tx {
rx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)>;
};
};
usart2_pins_a: usart2@0 {
rx_tx {
rx = <STM32_PIN_PA3 (STM32_PINMUX_ALT_FUNC_4 | STM32_PUPDR_NO_PULL)>;
tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_4 | STM32_PUSHPULL_NOPULL)>;
};
};
};
};
};

86
dts/arm/st/stm32l0.dtsi Normal file
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@ -0,0 +1,86 @@
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/stm32l0-pinctrl.dtsi>
#include <arm/armv6-m.dtsi>
#include <st/mem.h>
#include <dt-bindings/clock/stm32_clock.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
flash-controller@40022000 {
compatible = "st,stm32l0-flash-controller";
label = "FLASH_CTRL";
reg = <0x40022000 0x400>;
interrupts = <3 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "soc-nv-flash";
label = "FLASH_STM32";
reg = <0x08000000 DT_FLASH_SIZE>;
write-block-size = <4>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
clocks-controller;
#clocks-cells = <2>;
reg = <0x40021000 0x400>;
label = "STM32_CLK_RCC";
};
pinctrl: pin-controller {
compatible = "st,stm32-pinmux";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x48000000 0x1800>;
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <27 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <28 0>;
status = "disabled";
label = "UART_2";
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};

7
dts/arm/st/stm32l072.dtsi Normal file
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@ -0,0 +1,7 @@
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/stm32l0.dtsi>