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aarch64: Use helpers instead of inline assembly

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No need to rely on inline assembly when helpers are available.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2021-02-12 13:58:06 +01:00 • committed by Anas Nashif
commit bba7abe975
5 changed files with 29 additions and 91 deletions
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29
include/arch/arm/aarch64/asm_inline_gcc.h
View file

@ -16,28 +16,13 @@
#ifndef _ASMLANGUAGE
#include <arch/arm/aarch64/cpu.h>
#include <arch/arm/aarch64/lib_helpers.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
static ALWAYS_INLINE void __DSB(void)
{
__asm__ volatile ("dsb sy" : : : "memory");
}
static ALWAYS_INLINE void __DMB(void)
{
__asm__ volatile ("dmb sy" : : : "memory");
}
static ALWAYS_INLINE void __ISB(void)
{
__asm__ volatile ("isb" : : : "memory");
}
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key;
@ -46,21 +31,15 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
* Return the whole DAIF register as key but use DAIFSET to disable
* IRQs.
*/
__asm__ volatile("mrs %0, daif;"
"msr daifset, %1;"
: "=r" (key)
: "i" (DAIFSET_IRQ_BIT)
: "memory");
key = read_daif();
disable_irq();
return key;
}
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
__asm__ volatile("msr daif, %0;"
:
: "r" (key)
: "memory");
write_daif(key);
}
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)

15
include/arch/arm/aarch64/cpu.h
View file

@ -201,19 +201,4 @@
#endif /* CONFIG_CPU_CORTEX_A72 */
#ifndef _ASMLANGUAGE
/* Core sysreg macros */
#define read_sysreg(reg) ({ \
uint64_t val; \
__asm__ volatile("mrs %0, " STRINGIFY(reg) : "=r" (val));\
val; \
})
#define write_sysreg(val, reg) ({ \
__asm__ volatile("msr " STRINGIFY(reg) ", %0" : : "r" (val));\
})
#endif /* !_ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_CPU_H_ */

26
include/arch/arm/aarch64/timer.h
View file

@ -26,16 +26,14 @@ static ALWAYS_INLINE void arm_arch_timer_init(void)
static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
{
__asm__ volatile("msr cntv_cval_el0, %0\n\t"
: : "r" (val) : "memory");
write_cntv_cval_el0(val);
}
static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
{
uint32_t cntv_ctl;
uint64_t cntv_ctl;
__asm__ volatile("mrs %0, cntv_ctl_el0\n\t"
: "=r" (cntv_ctl) : : "memory");
cntv_ctl = read_cntv_ctl_el0();
if (enable) {
cntv_ctl |= CNTV_CTL_ENABLE_BIT;
@ -43,16 +41,14 @@ static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
}
__asm__ volatile("msr cntv_ctl_el0, %0\n\t"
: : "r" (cntv_ctl) : "memory");
write_cntv_ctl_el0(cntv_ctl);
}
static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
{
uint32_t cntv_ctl;
uint64_t cntv_ctl;
__asm__ volatile("mrs %0, cntv_ctl_el0\n\t"
: "=r" (cntv_ctl) : : "memory");
cntv_ctl = read_cntv_ctl_el0();
if (mask) {
cntv_ctl |= CNTV_CTL_IMASK_BIT;
@ -60,18 +56,12 @@ static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
}
__asm__ volatile("msr cntv_ctl_el0, %0\n\t"
: : "r" (cntv_ctl) : "memory");
write_cntv_ctl_el0(cntv_ctl);
}
static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
{
uint64_t cntvct_el0;
__asm__ volatile("mrs %0, cntvct_el0\n\t"
: "=r" (cntvct_el0) : : "memory");
return cntvct_el0;
return read_cntvct_el0();
}
#ifdef __cplusplus