drivers: intc: irqstr: change name of level1 IRQ enable/disable

Add the "_raw" suffix to the macros handling the level 1 IRQ enable and
disable operation to signify that these operations perform no refcounting.
Additionally, shorten some portions of the name.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2025-04-15 12:49:22 +03:00 committed by Benjamin Cabé
commit bb7efcf03b

View file

@ -266,12 +266,12 @@ LOG_MODULE_REGISTER(nxp_irqstr);
(((const struct irqsteer_config *)disp->dev->config)->regmap_phys) (((const struct irqsteer_config *)disp->dev->config)->regmap_phys)
#if defined(CONFIG_XTENSA) #if defined(CONFIG_XTENSA)
#define irqsteer_level1_irq_enable(irq) xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)) #define irqstr_l1_irq_enable_raw(irq) xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq))
#define irqsteer_level1_irq_disable(irq) xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)) #define irqstr_l1_irq_disable_raw(irq) xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq))
#define irqsteer_level1_irq_is_enabled(irq) xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)) #define irqsteer_level1_irq_is_enabled(irq) xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq))
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#define irqsteer_level1_irq_enable(irq) arm_irq_enable(irq) #define irqstr_l1_irq_enable_raw(irq) arm_irq_enable(irq)
#define irqsteer_level1_irq_disable(irq) arm_irq_disable(irq) #define irqstr_l1_irq_disable_raw(irq) arm_irq_disable(irq)
#define irqsteer_level1_irq_is_enabled(irq) arm_irq_is_enabled(irq) #define irqsteer_level1_irq_is_enabled(irq) arm_irq_is_enabled(irq)
#else #else
#error ARCH not supported #error ARCH not supported
@ -348,11 +348,11 @@ static void _irqstr_disp_enable_disable(struct irqsteer_dispatcher *disp,
uint32_t regmap = DISPATCHER_REGMAP(disp); uint32_t regmap = DISPATCHER_REGMAP(disp);
if (enable) { if (enable) {
irqsteer_level1_irq_enable(disp->irq); irqstr_l1_irq_enable_raw(disp->irq);
IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq); IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq);
} else { } else {
IRQSTEER_DisableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq); IRQSTEER_DisableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq);
irqsteer_level1_irq_disable(disp->irq); irqstr_l1_irq_disable_raw(disp->irq);
} }
} }
@ -477,9 +477,9 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
if (irq_get_level(irq) == 1) { if (irq_get_level(irq) == 1) {
/* LEVEL 1 interrupts are DSP direct */ /* LEVEL 1 interrupts are DSP direct */
if (enable) { if (enable) {
irqsteer_level1_irq_enable(irq); irqstr_l1_irq_enable_raw(irq);
} else { } else {
irqsteer_level1_irq_disable(irq); irqstr_l1_irq_disable_raw(irq);
} }
return; return;
} }