riscv_machine_timer: optimize MTIME/MTIMECMP registers access in riscv64
riscv64 CPUs can access full 64-bit memory-mapped register by a single instruction, so we can directly access these registers. Signed-off-by: Jim Shu <cwshu@andestech.com>
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1 changed files with 8 additions and 0 deletions
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@ -22,6 +22,9 @@ static u64_t last_count;
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static void set_mtimecmp(u64_t time)
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{
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#ifdef CONFIG_64BIT
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*(volatile u64_t *)RISCV_MTIMECMP_BASE = time;
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#else
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volatile u32_t *r = (u32_t *)RISCV_MTIMECMP_BASE;
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/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
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@ -33,10 +36,14 @@ static void set_mtimecmp(u64_t time)
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r[1] = 0xffffffff;
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r[0] = (u32_t)time;
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r[1] = (u32_t)(time >> 32);
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#endif
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}
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static u64_t mtime(void)
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{
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#ifdef CONFIG_64BIT
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return *(volatile u64_t *)RISCV_MTIME_BASE;
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#else
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volatile u32_t *r = (u32_t *)RISCV_MTIME_BASE;
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u32_t lo, hi;
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@ -47,6 +54,7 @@ static u64_t mtime(void)
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} while (r[1] != hi);
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return (((u64_t)hi) << 32) | lo;
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#endif
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}
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static void timer_isr(void *arg)
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