From ba9ade9df69deb9943fc3e8d590de01f4767ce08 Mon Sep 17 00:00:00 2001 From: Maciej Debski Date: Wed, 9 Aug 2017 11:21:09 +0200 Subject: [PATCH] dts: arm: provide support for nucleo f030r8. Fixes #3923 Signed-off-by: Maciej Debski Signed-off-by: Neil Armstrong --- dts/arm/Makefile | 9 +++-- dts/arm/nucleo_f030r8.dts | 33 +++++++++++++++ dts/arm/nucleo_f030r8.fixup | 14 +++++++ dts/arm/st/mem.h | 5 ++- dts/arm/st/stm32f0-pinctrl.dtsi | 38 +++++++++++++++++ dts/arm/st/stm32f0.dtsi | 72 +++++++++++++++++++++++++++++++++ dts/arm/st/stm32f030.dtsi | 7 ++++ 7 files changed, 173 insertions(+), 5 deletions(-) create mode 100644 dts/arm/nucleo_f030r8.dts create mode 100644 dts/arm/nucleo_f030r8.fixup create mode 100644 dts/arm/st/stm32f0-pinctrl.dtsi create mode 100644 dts/arm/st/stm32f0.dtsi create mode 100644 dts/arm/st/stm32f030.dtsi diff --git a/dts/arm/Makefile b/dts/arm/Makefile index a4843c7373b..a60fff186f5 100644 --- a/dts/arm/Makefile +++ b/dts/arm/Makefile @@ -7,22 +7,23 @@ dtb-$(CONFIG_BOARD_HEXIWEAR_K64) = hexiwear_k64.dts_compiled dtb-$(CONFIG_BOARD_HEXIWEAR_KW40Z) = hexiwear_kw40z.dts_compiled dtb-$(CONFIG_BOARD_USB_KW24D512) = usb_kw24d512.dts_compiled dtb-$(CONFIG_BOARD_CC3220SF_LAUNCHXL) = cc3220sf_launchxl.dts_compiled -dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled -dtb-$(CONFIG_BOARD_NUCLEO_L432KC) = nucleo_l432kc.dts_compiled dtb-$(CONFIG_BOARD_V2M_BEETLE) = v2m_beetle.dts_compiled dtb-$(CONFIG_BOARD_MPS2_AN385) = mps2_an385.dts_compiled dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled dtb-$(CONFIG_BOARD_96B_CARBON) = 96b_carbon.dts_compiled dtb-$(CONFIG_BOARD_96B_CARBON_NRF51) = 96b_carbon_nrf51.dts_compiled +dtb-$(CONFIG_BOARD_NUCLEO_F030R8) = nucleo_f030r8.dts_compiled +dtb-$(CONFIG_BOARD_NUCLEO_F103RB) = nucleo_f103rb.dts_compiled +dtb-$(CONFIG_BOARD_NUCLEO_F334R8) = nucleo_f334r8.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F401RE) = nucleo_f401re.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F411RE) = nucleo_f411re.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F412ZG) = nucleo_f412zg.dts_compiled dtb-$(CONFIG_BOARD_NUCLEO_F413ZH) = nucleo_f413zh.dts_compiled -dtb-$(CONFIG_BOARD_NUCLEO_F103RB) = nucleo_f103rb.dts_compiled +dtb-$(CONFIG_BOARD_NUCLEO_L432KC) = nucleo_l432kc.dts_compiled +dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled dtb-$(CONFIG_BOARD_STM3210C_EVAL) = stm3210c_eval.dts_compiled dtb-$(CONFIG_BOARD_STM32_MINI_A15) = stm32_mini_a15.dts_compiled dtb-$(CONFIG_BOARD_STM32L496G_DISCO) = stm32l496g_disco.dts_compiled -dtb-$(CONFIG_BOARD_NUCLEO_F334R8) = nucleo_f334r8.dts_compiled dtb-$(CONFIG_BOARD_STM32373C_EVAL) = stm32373c_eval.dts_compiled dtb-$(CONFIG_BOARD_STM32F4_DISCO) = stm32f4_disco.dts_compiled dtb-$(CONFIG_BOARD_STM32F469I_DISCO) = stm32f469i_disco.dts_compiled diff --git a/dts/arm/nucleo_f030r8.dts b/dts/arm/nucleo_f030r8.dts new file mode 100644 index 00000000000..d0d6bb67dc7 --- /dev/null +++ b/dts/arm/nucleo_f030r8.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2017 RnDity Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "STMicroelectronics STM32F030R8-NUCLEO board"; + compatible = "st,stm32f030r8-nucleo", "st,stm32f030"; + + chosen { + zephyr,console = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&usart1 { + current-speed = <115200>; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "ok"; +}; + +&usart2 { + current-speed = <115200>; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-names = "default"; + status = "ok"; +}; diff --git a/dts/arm/nucleo_f030r8.fixup b/dts/arm/nucleo_f030r8.fixup new file mode 100644 index 00000000000..06daaf9e70a --- /dev/null +++ b/dts/arm/nucleo_f030r8.fixup @@ -0,0 +1,14 @@ +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + + +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS +#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED +#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define CONFIG_UART_STM32_PORT_2_NAME ST_STM32_USART_40004400_LABEL +#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0 diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h index 6ae4263311c..0e5a50e8dc4 100644 --- a/dts/arm/st/mem.h +++ b/dts/arm/st/mem.h @@ -8,7 +8,10 @@ #define __SIZE_K(x) (x * 1024) -#if defined(CONFIG_SOC_STM32F103X8) +#if defined(CONFIG_SOC_STM32F030X8) +#define DT_FLASH_SIZE __SIZE_K(64) +#define DT_SRAM_SIZE __SIZE_K(8) +#elif defined(CONFIG_SOC_STM32F103X8) #define DT_FLASH_SIZE __SIZE_K(64) #define DT_SRAM_SIZE __SIZE_K(20) #elif defined(CONFIG_SOC_STM32F103XB) diff --git a/dts/arm/st/stm32f0-pinctrl.dtsi b/dts/arm/st/stm32f0-pinctrl.dtsi new file mode 100644 index 00000000000..bfc37823bd2 --- /dev/null +++ b/dts/arm/st/stm32f0-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017 RnDity Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + pinctrl: pin-controller { + usart1_pins_a: usart1@0 { + rx_tx { + rx = ; + tx = ; + }; + }; + usart1_pins_b: usart1@1 { + rx_tx { + rx = ; + tx = ; + }; + }; + usart2_pins_a: usart2@0 { + rx_tx { + rx = ; + tx = ; + }; + }; + usart2_pins_b: usart2@1 { + rx_tx { + rx = ; + tx = ; + }; + }; + }; + }; +}; diff --git a/dts/arm/st/stm32f0.dtsi b/dts/arm/st/stm32f0.dtsi new file mode 100644 index 00000000000..d14580bbb66 --- /dev/null +++ b/dts/arm/st/stm32f0.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2017 RnDity Sp. z o.o. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m0"; + reg = <0>; + }; + }; + flash0: flash@8000000 { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + rcc: rcc@40021000 { + compatible = "st,stm32-rcc"; + clocks-controller; + #clocks-cells = <2>; + reg = <0x40021000 0x400>; + label = "STM32_CLK_RCC"; + }; + + pinctrl: pin-controller { + compatible = "st,stm32-pinmux"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x48000000 0x1800>; + }; + + usart1: serial@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>; + interrupts = <27 0>; + status = "disabled"; + label = "UART_1"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; + interrupts = <28 0>; + status = "disabled"; + label = "UART_2"; + }; + + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/dts/arm/st/stm32f030.dtsi b/dts/arm/st/stm32f030.dtsi new file mode 100644 index 00000000000..cd28d1d32ff --- /dev/null +++ b/dts/arm/st/stm32f030.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include