imx: Add IMX IPM driver for i.MX socs
Add driver for i.MX Messaging Unit peripheral which can be used for i.MX6SoloX, i.MX7D and other i.MX socs. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This commit is contained in:
Stanislav Poboril
Kumar Gala
parent
1bf1d6a267
commit
ba3ed24f3d
5 changed files with 327 additions and 0 deletions
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@ -1,6 +1,7 @@
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_IPM_MCUX ipm_mcux.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_IMX ipm_imx.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_QUARK_SE ipm_quark_se.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE ipm_handlers.c)
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@ -23,3 +23,55 @@ config IPM_MCUX
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depends on IPM && HAS_MCUX
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help
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Driver for MCUX mailbox
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config IPM_IMX
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bool "IMX IPM driver"
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default n
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depends on IPM && HAS_IMX_HAL
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help
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Driver for NXP i.MX messaging unit
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choice
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prompt "IMX IPM max data size"
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default IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX
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help
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Select maximum message size for NXP i.MX messaging unit.
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config IPM_IMX_MAX_DATA_SIZE_4
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bool "4 bytes"
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help
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There will be four message types with ids 0, 1, 2 or 3
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and a maximum size of 4 bytes each.
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config IPM_IMX_MAX_DATA_SIZE_8
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bool "8 bytes"
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help
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There will be two message types with ids 0 or 1
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and a maximum size of 8 bytes each.
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config IPM_IMX_MAX_DATA_SIZE_16
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bool "16 bytes"
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help
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There will be a single message type with id 0
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and a maximum size of 16 bytes.
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endchoice
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config IPM_IMX_MAX_DATA_SIZE
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int
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range 4 16
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# omit prompt to signify a "hidden" option
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default 4 if IPM_IMX_MAX_DATA_SIZE_4
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default 8 if IPM_IMX_MAX_DATA_SIZE_8
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default 16 if IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX
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config IPM_IMX_MAX_ID_VAL
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int
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range 0 3
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# omit prompt to signify a "hidden" option
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default 3 if IPM_IMX_MAX_DATA_SIZE_4
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default 1 if IPM_IMX_MAX_DATA_SIZE_8
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default 0 if IPM_IMX_MAX_DATA_SIZE_16
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depends on IPM_IMX
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229
drivers/ipm/ipm_imx.c
Normal file
229
drivers/ipm/ipm_imx.c
Normal file
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@ -0,0 +1,229 @@
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/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <string.h>
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#include <device.h>
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#include <soc.h>
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#include <ipm.h>
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#include <mu_imx.h>
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#define MU(config) ((MU_Type *)config->base)
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#if ((CONFIG_IPM_IMX_MAX_DATA_SIZE % 4) != 0)
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#error CONFIG_IPM_IMX_MAX_DATA_SIZE is invalid
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#endif
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#define IMX_IPM_DATA_REGS (CONFIG_IPM_IMX_MAX_DATA_SIZE / 4)
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struct imx_mu_config {
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MU_Type *base;
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void (*irq_config_func)(struct device *dev);
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};
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struct imx_mu_data {
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ipm_callback_t callback;
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void *callback_ctx;
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};
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static void imx_mu_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct imx_mu_config *config = dev->config->config_info;
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MU_Type *base = MU(config);
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struct imx_mu_data *data = dev->driver_data;
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u32_t data32[IMX_IPM_DATA_REGS];
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u32_t status_reg;
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s32_t id;
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s32_t i;
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bool all_registers_full;
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status_reg = base->SR >>= MU_SR_RFn_SHIFT;
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for (id = CONFIG_IPM_IMX_MAX_ID_VAL; id >= 0; id--) {
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if (status_reg & 0x1U) {
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/*
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* Check if all receive registers are full. If not,
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* it is violation of the protocol (status register
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* are set earlier than all receive registers).
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* Do not read any of the registers in such situation.
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*/
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all_registers_full = true;
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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if (!MU_IsRxFull(base,
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(id * IMX_IPM_DATA_REGS) + i)) {
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all_registers_full = false;
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break;
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}
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}
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if (all_registers_full) {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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MU_ReceiveMsg(base,
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(id * IMX_IPM_DATA_REGS) + i,
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&data32[i]);
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}
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if (data->callback) {
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data->callback(data->callback_ctx,
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(u32_t)id,
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&data32[0]);
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}
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}
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}
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status_reg >>= IMX_IPM_DATA_REGS;
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
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* Store immediate overlapping exception return operation
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* might vector to incorrect interrupt
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*/
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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static int imx_mu_ipm_send(struct device *dev, int wait, u32_t id,
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const void *data, int size)
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{
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const struct imx_mu_config *config = dev->config->config_info;
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MU_Type *base = MU(config);
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u32_t data32[IMX_IPM_DATA_REGS];
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mu_status_t status;
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int i;
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if (id > CONFIG_IPM_IMX_MAX_ID_VAL) {
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return -EINVAL;
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}
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if (size > CONFIG_IPM_IMX_MAX_DATA_SIZE) {
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return -EMSGSIZE;
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}
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/* Actual message is passing using 32 bits registers */
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memcpy(data32, data, size);
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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status = MU_TrySendMsg(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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if (status == kStatus_MU_TxNotEmpty) {
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return -EBUSY;
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}
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}
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if (wait) {
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while (!MU_IsTxEmpty(base,
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(id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
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}
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}
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return 0;
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}
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static int imx_mu_ipm_max_data_size_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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return CONFIG_IPM_IMX_MAX_DATA_SIZE;
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}
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static u32_t imx_mu_ipm_max_id_val_get(struct device *dev)
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{
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ARG_UNUSED(dev);
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return CONFIG_IPM_IMX_MAX_ID_VAL;
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}
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static void imx_mu_ipm_register_callback(struct device *dev,
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ipm_callback_t cb,
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void *context)
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{
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struct imx_mu_data *driver_data = dev->driver_data;
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driver_data->callback = cb;
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driver_data->callback_ctx = context;
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}
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static int imx_mu_ipm_set_enabled(struct device *dev, int enable)
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{
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const struct imx_mu_config *config = dev->config->config_info;
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MU_Type *base = MU(config);
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#if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
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if (enable) {
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MU_EnableRxFullInt(base, 0U);
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MU_EnableRxFullInt(base, 1U);
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MU_EnableRxFullInt(base, 2U);
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 0U);
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MU_DisableRxFullInt(base, 1U);
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MU_DisableRxFullInt(base, 2U);
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MU_DisableRxFullInt(base, 3U);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
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if (enable) {
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MU_EnableRxFullInt(base, 1U);
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 1U);
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MU_DisableRxFullInt(base, 3U);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
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if (enable) {
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MU_EnableRxFullInt(base, 3U);
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} else {
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MU_DisableRxFullInt(base, 3U);
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}
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#else
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#error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
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#endif
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return 0;
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}
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static int imx_mu_init(struct device *dev)
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{
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const struct imx_mu_config *config = dev->config->config_info;
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MU_Init(MU(config));
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config->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api imx_mu_driver_api = {
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.send = imx_mu_ipm_send,
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.register_callback = imx_mu_ipm_register_callback,
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.max_data_size_get = imx_mu_ipm_max_data_size_get,
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.max_id_val_get = imx_mu_ipm_max_id_val_get,
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.set_enabled = imx_mu_ipm_set_enabled
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};
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/* Config MU */
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static void imx_mu_config_func_b(struct device *dev);
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static const struct imx_mu_config imx_mu_b_config = {
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.base = (MU_Type *)DT_IPM_IMX_MU_B_BASE_ADDRESS,
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.irq_config_func = imx_mu_config_func_b,
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};
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static struct imx_mu_data imx_mu_b_data;
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DEVICE_AND_API_INIT(mu_b, DT_IPM_IMX_MU_B_NAME,
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&imx_mu_init,
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&imx_mu_b_data, &imx_mu_b_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_mu_driver_api);
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static void imx_mu_config_func_b(struct device *dev)
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{
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IRQ_CONNECT(DT_IPM_IMX_MU_B_IRQ,
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DT_IPM_IMX_MU_B_IRQ_PRI,
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imx_mu_isr, DEVICE_GET(mu_b), 0);
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irq_enable(DT_IPM_IMX_MU_B_IRQ);
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}
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44
dts/bindings/arm/nxp,imx-mu.yaml
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44
dts/bindings/arm/nxp,imx-mu.yaml
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@ -0,0 +1,44 @@
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#
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# Copyright (c) 2018, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: IMX MESSAGING UNIT
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version: 0.1
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description: >
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This binding gives a base representation of the i.MX Messaging Unit
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "nxp,imx-mu"
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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label:
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type: string
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category: required
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description: Human readable string describing the device (used by Zephyr for API name)
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generation: define
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rdc:
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type: int
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category: required
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description: Set the RDC permission for this peripheral
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generation: define
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...
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@ -13,3 +13,4 @@ endif()
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zephyr_sources_ifdef(CONFIG_UART_IMX uart_imx.c)
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zephyr_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c)
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zephyr_sources_ifdef(CONFIG_I2C_IMX i2c_imx.c)
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zephyr_sources_ifdef(CONFIG_IPM_IMX mu_imx.c)
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