driver: PS/2: npcx: add driver support for Nuvoton npcx family
The PS/2 module in npcx provides a hardware accelerator mechanism including an 8-bit shift register, a state machine, and control logic that handle both the incoming and outgoing data. The hardware accelerator mechanism is shared by 4 PS/2 channels. To support it, this CL separates the PS/2 driver into channel and controller drivers. The controller driver is in charge of the PS/2 transaction. The channel driver is in charge of the connection between the Zehpyr PS/2 API interface and controller driver. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit is contained in:
Jun Lin
Anas Nashif
parent
8e4d9ae2e8
commit
ba39c47187
11 changed files with 755 additions and 0 deletions
373
drivers/ps2/ps2_npcx_controller.c
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373
drivers/ps2/ps2_npcx_controller.c
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_ps2_ctrl
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/**
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* @file
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* @brief Nuvoton NPCX PS/2 module (controller) driver
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*
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* This file contains the driver of PS/2 module (controller) which provides a
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* hardware accelerator mechanism to handle both incoming and outgoing data.
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* The hardware accelerator mechanism is shared by four PS/2 channels.
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*/
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#include <drivers/clock_control.h>
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#include <drivers/ps2.h>
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#include <dt-bindings/clock/npcx_clock.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ps2_npcx_ctrl, CONFIG_PS2_LOG_LEVEL);
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#define NPCX_PS2_CH_COUNT 4
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/*
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* Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
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* reset the shift mechanism.
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*/
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#define NPCX_PS2_SHIFT_MECH_RESET (uint8_t)~NPCX_PSOSIG_CLK_MASK_ALL
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/* in 50us units */
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#define PS2_RETRY_COUNT 10000
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/*
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* The max duration of a PS/2 clock is about 100 micro-seconds.
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* A PS/2 transaction needs 11 clock cycles. It will take about 1.1 ms for a
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* complete transaction.
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*/
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#define PS2_TRANSACTION_TIMEOUT K_MSEC(2)
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/* Device config */
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struct ps2_npcx_ctrl_config {
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uintptr_t base;
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struct npcx_clk_cfg clk_cfg;
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};
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/* Driver data */
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struct ps2_npcx_ctrl_data {
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/*
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* Bit mask to record the enabled PS/2 channels.
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* Only bit[7] and bit[5:3] are used
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* (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
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*/
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uint8_t channel_enabled_mask;
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/* The mutex of the PS/2 controller */
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struct k_sem lock;
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/* The semaphore to synchronize the Tx transaction */
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struct k_sem tx_sync_sem;
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/*
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* The callback function to handle the data received from PS/2 device
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*/
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ps2_callback_t callback_isr[NPCX_PS2_CH_COUNT];
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct ps2_npcx_ctrl_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct ps2_npcx_ctrl_data *)(dev)->data)
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#define HAL_PS2_INSTANCE(dev) (struct ps2_reg *)(DRV_CONFIG(dev)->base)
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static uint8_t ps2_npcx_ctrl_get_ch_clk_mask(uint8_t channel_id)
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{
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return BIT(NPCX_PSOSIG_CLK(channel_id));
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}
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int ps2_npcx_ctrl_configure(const struct device *dev, uint8_t channel_id,
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ps2_callback_t callback_isr)
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{
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struct ps2_npcx_ctrl_data *const data = DRV_DATA(dev);
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if (channel_id >= NPCX_PS2_CH_COUNT) {
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LOG_ERR("unexpected channel ID: %d", channel_id);
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return -EINVAL;
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}
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if (callback_isr == NULL) {
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return -EINVAL;
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}
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k_sem_take(&data->lock, K_FOREVER);
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data->callback_isr[channel_id] = callback_isr;
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k_sem_give(&data->lock);
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return 0;
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}
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int ps2_npcx_ctrl_enable_interface(const struct device *dev, uint8_t channel_id,
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bool enable)
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{
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struct ps2_npcx_ctrl_data *const data = DRV_DATA(dev);
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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uint8_t ch_clk_mask;
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k_sem_take(&data->lock, K_FOREVER);
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/*
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* Disable the interrupt during changing the enabled channel mask to
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* prevent from preemption.
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*/
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irq_disable(DT_INST_IRQN(0));
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if (channel_id >= NPCX_PS2_CH_COUNT) {
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LOG_ERR("unexpected channel ID: %d", channel_id);
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irq_enable(DT_INST_IRQN(0));
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k_sem_give(&data->lock);
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return -EINVAL;
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}
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ch_clk_mask = ps2_npcx_ctrl_get_ch_clk_mask(channel_id);
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if (enable) {
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data->channel_enabled_mask |= ch_clk_mask;
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/* Enable the relevant channel clock */
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inst->PSOSIG |= ch_clk_mask;
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} else {
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data->channel_enabled_mask &= ~ch_clk_mask;
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/* Disable the relevant channel clock */
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inst->PSOSIG &= ~ch_clk_mask;
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}
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irq_enable(DT_INST_IRQN(0));
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k_sem_give(&data->lock);
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return 0;
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}
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static int ps2_npcx_ctrl_bus_busy(const struct device *dev)
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{
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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/*
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* The driver pulls the CLK for non-active channels to low when Start
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* bit is detected and pull the CLK of the active channel low after
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* Stop bit detected. The EOT bit is set when Stop bit is detected,
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* but both SOT and EOT are cleared when all CLKs are pull low
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* (due to Shift Mechanism is reset)
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*/
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return (IS_BIT_SET(inst->PSTAT, NPCX_PSTAT_SOT) ||
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IS_BIT_SET(inst->PSTAT, NPCX_PSTAT_EOT)) ?
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-EBUSY :
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0;
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}
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int ps2_npcx_ctrl_write(const struct device *dev, uint8_t channel_id,
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uint8_t value)
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{
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struct ps2_npcx_ctrl_data *const data = DRV_DATA(dev);
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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int i = 0;
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if (channel_id >= NPCX_PS2_CH_COUNT) {
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LOG_ERR("unexpected channel ID: %d", channel_id);
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return -EINVAL;
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}
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if (!(ps2_npcx_ctrl_get_ch_clk_mask(channel_id) &
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data->channel_enabled_mask)) {
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LOG_ERR("channel %d is not enabled", channel_id);
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return -EINVAL;
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}
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k_sem_take(&data->lock, K_FOREVER);
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while (ps2_npcx_ctrl_bus_busy(dev) && (i < PS2_RETRY_COUNT)) {
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k_busy_wait(50);
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i++;
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}
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if (unlikely(i == PS2_RETRY_COUNT)) {
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LOG_ERR("PS2 write attempt timed out");
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goto timeout_invalid;
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}
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/* Set PS/2 in transmit mode */
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inst->PSCON |= BIT(NPCX_PSCON_XMT);
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/* Enable Start Of Transaction interrupt */
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inst->PSIEN |= BIT(NPCX_PSIEN_SOTIE);
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/* Reset the shift mechanism */
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inst->PSOSIG = NPCX_PS2_SHIFT_MECH_RESET;
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/* Inhibit communication should last at least 100 micro-seconds */
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k_busy_wait(100);
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/* Write the data to be transmitted */
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inst->PSDAT = value;
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/* Apply the Request-to-send */
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inst->PSOSIG &= ~BIT(NPCX_PSOSIG_WDAT(channel_id));
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inst->PSOSIG |= ps2_npcx_ctrl_get_ch_clk_mask(channel_id);
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if (k_sem_take(&data->tx_sync_sem, PS2_TRANSACTION_TIMEOUT) != 0) {
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irq_disable(DT_INST_IRQN(0));
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LOG_ERR("PS/2 Tx timeout");
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/* Reset the shift mechanism */
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inst->PSOSIG = NPCX_PS2_SHIFT_MECH_RESET;
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/* Change the PS/2 module to receive mode */
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inst->PSCON &= ~BIT(NPCX_PSCON_XMT);
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/*
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* Restore the channel back to enable according to
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* channel_enabled_mask.
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*/
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inst->PSOSIG |= data->channel_enabled_mask;
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irq_enable(DT_INST_IRQN(0));
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goto timeout_invalid;
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}
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k_sem_give(&data->lock);
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return 0;
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timeout_invalid:
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k_sem_give(&data->lock);
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return -ETIMEDOUT;
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}
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static int ps2_npcx_ctrl_is_rx_error(const struct device *dev)
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{
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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uint8_t status;
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status = inst->PSTAT & (BIT(NPCX_PSTAT_PERR) | BIT(NPCX_PSTAT_RFERR));
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if (status) {
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if (status & BIT(NPCX_PSTAT_PERR))
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LOG_ERR("RX parity error");
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if (status & BIT(NPCX_PSTAT_RFERR))
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LOG_ERR("RX Frame error");
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return -EIO;
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}
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return 0;
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}
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static void ps2_npcx_ctrl_isr(const struct device *dev)
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{
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uint8_t active_ch, mask;
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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struct ps2_npcx_ctrl_data *const data = DRV_DATA(dev);
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/*
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* ACH = 1 : Channel 0
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* ACH = 2 : Channel 1
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* ACH = 4 : Channel 2
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* ACH = 5 : Channel 3
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*/
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active_ch = GET_FIELD(inst->PSTAT, NPCX_PSTAT_ACH);
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active_ch = active_ch > 2 ? (active_ch - 2) : (active_ch - 1);
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LOG_DBG("ACH: %d\n", active_ch);
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/*
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* Inhibit PS/2 transaction of the other non-active channels by
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* pulling down the clock signal
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*/
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mask = ~NPCX_PSOSIG_CLK_MASK_ALL | BIT(NPCX_PSOSIG_CLK(active_ch));
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inst->PSOSIG &= mask;
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/* PS/2 Start of Transaction */
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if (IS_BIT_SET(inst->PSTAT, NPCX_PSTAT_SOT) &&
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IS_BIT_SET(inst->PSIEN, NPCX_PSIEN_SOTIE)) {
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/*
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* Once set, SOT is not cleared until the shift mechanism
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* is reset. Therefore, SOTIE should be cleared on the
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* first occurrence of an SOT interrupt.
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*/
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inst->PSIEN &= ~BIT(NPCX_PSIEN_SOTIE);
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LOG_DBG("SOT");
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/* PS/2 End of Transaction */
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} else if (IS_BIT_SET(inst->PSTAT, NPCX_PSTAT_EOT)) {
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inst->PSIEN &= ~BIT(NPCX_PSIEN_EOTIE);
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/*
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* Clear the CLK of active channel to reset
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* the shift mechanism
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*/
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inst->PSOSIG &= ~BIT(NPCX_PSOSIG_CLK(active_ch));
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/* Tx is done */
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if (IS_BIT_SET(inst->PSCON, NPCX_PSCON_XMT)) {
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/* Change the PS/2 module to receive mode */
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inst->PSCON &= ~BIT(NPCX_PSCON_XMT);
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k_sem_give(&data->tx_sync_sem);
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} else {
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if (ps2_npcx_ctrl_is_rx_error(dev) == 0) {
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ps2_callback_t callback;
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uint8_t data_in = inst->PSDAT;
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LOG_DBG("Recv:0x%02x", data_in);
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callback = data->callback_isr[active_ch];
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if (callback != NULL)
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callback(dev, data_in);
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}
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}
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/* Restore the enabled channel */
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inst->PSOSIG |= data->channel_enabled_mask;
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/*
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* Re-enable the Start Of Transaction interrupt when
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* the shift mechanism is reset
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*/
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inst->PSIEN |= BIT(NPCX_PSIEN_SOTIE);
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inst->PSIEN |= BIT(NPCX_PSIEN_EOTIE);
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LOG_DBG("EOT");
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}
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}
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/* PS/2 driver registration */
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static int ps2_npcx_ctrl_init(const struct device *dev);
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static struct ps2_npcx_ctrl_data ps2_npcx_ctrl_data_0;
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static const struct ps2_npcx_ctrl_config ps2_npcx_ctrl_config_0 = {
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.base = DT_INST_REG_ADDR(0),
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.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
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};
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DEVICE_DT_INST_DEFINE(0, &ps2_npcx_ctrl_init, NULL, &ps2_npcx_ctrl_data_0,
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&ps2_npcx_ctrl_config_0, POST_KERNEL,
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CONFIG_PS2_INIT_PRIORITY, NULL);
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static int ps2_npcx_ctrl_init(const struct device *dev)
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{
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const struct ps2_npcx_ctrl_config *const config = DRV_CONFIG(dev);
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struct ps2_npcx_ctrl_data *const data = DRV_DATA(dev);
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struct ps2_reg *const inst = HAL_PS2_INSTANCE(dev);
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const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME);
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int ret;
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/* Turn on PS/2 controller device clock */
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ret = clock_control_on(clk_dev,
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(clock_control_subsys_t *)&config->clk_cfg);
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if (ret < 0) {
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LOG_ERR("Turn on PS/2 clock fail %d", ret);
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return ret;
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}
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/* Disable shift mechanism and configure PS/2 to received mode. */
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inst->PSCON = 0x0;
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/* Set WDAT3-0 and clear CLK3-0 before enabling shift mechanism */
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inst->PSOSIG = NPCX_PS2_SHIFT_MECH_RESET;
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/*
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* PS/2 interrupt enable register
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* [0] - : SOTIE = 1: Start Of Transaction Interrupt Enable
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* [1] - : EOTIE = 1: End Of Transaction Interrupt Enable
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* [4] - : WUE = 1: Wake-Up Enable
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* [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock
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* 0: Select APB1 clock as the basic clock
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*/
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inst->PSIEN = BIT(NPCX_PSIEN_SOTIE) | BIT(NPCX_PSIEN_EOTIE) |
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BIT(NPCX_PSIEN_PS2_WUE);
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if (config->clk_cfg.bus == NPCX_CLOCK_BUS_FREERUN)
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inst->PSIEN |= BIT(NPCX_PSIEN_PS2_CLK_SEL);
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/* Enable weak internal pull-up */
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inst->PSCON |= BIT(NPCX_PSCON_WPUED);
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/* Enable shift mechanism */
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inst->PSCON |= BIT(NPCX_PSCON_EN);
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k_sem_init(&data->lock, 1, 1);
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k_sem_init(&data->tx_sync_sem, 0, 1);
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
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ps2_npcx_ctrl_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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