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soc/intel_adsp: bump core count to four for TGPLP cAVS builds

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With addition of separate intel_adsp_cavs25_tgph board to
cover 2 core variants, we can now bump the core count to
four cores for intel_adsp_cavs25 (used in Tiger Lake LP PCH).

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit is contained in:
Kai Vehmanen 2022-02-28 12:53:12 +02:00 • committed by Anas Nashif
commit ba02864d41
1 changed files with 2 additions and 0 deletions
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boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig
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@ -19,3 +19,5 @@ CONFIG_CAVS_ICTL=y
CONFIG_BOOTLOADER_SRAM_SIZE=192
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_CLEANUP_INTERMEDIATE_FILES=y
CONFIG_MP_NUM_CPUS=4