diff --git a/ext/hal/microchip/mec/mec1501/MEC1501hsz.h b/ext/hal/microchip/mec/mec1501/MEC1501hsz.h
index cd85aed5b25..595183c77a7 100644
--- a/ext/hal/microchip/mec/mec1501/MEC1501hsz.h
+++ b/ext/hal/microchip/mec/mec1501/MEC1501hsz.h
@@ -439,6 +439,7 @@ typedef enum IRQn {
 #include "component/espi_io.h"
 #include "component/espi_mem.h"
 #include "component/espi_vw.h"
+#include "component/global_cfg.h"
 #include "component/i2c.h"
 #include "component/kbc.h"
 #include "component/keyscan.h"
@@ -447,6 +448,7 @@ typedef enum IRQn {
 #include "component/pcr.h"
 #include "component/port80cap.h"
 #include "component/port92.h"
+#include "component/ps2_ctrl.h"
 #include "component/smb.h"
 #include "component/tfdp.h"
 #include "component/timer.h"
@@ -494,6 +496,9 @@ typedef enum IRQn {
 
 #define TFDP_REGS	((TFDP_Type *) TFDP_BASE)
 
+#define PS2_0_REGS	((PS2_Type *) PS2_0_BASE)
+#define PS2_1_REGS	((PS2_Type *) PS2_1_BASE)
+
 #define HTMR0_REGS      ((HTMR_Type *) HTMR0_BASE)
 #define HTMR1_REGS      ((HTMR_Type *) HTMR1_BASE)
 
@@ -584,6 +589,8 @@ typedef enum IRQn {
 #define PORT80_CAP0_REGS	((PORT80_CAP_Type *)(P80CAP0_BASE))
 #define PORT80_CAP1_REGS	((PORT80_CAP_Type *)(P80CAP1_BASE))
 
+#define GLOBAL_CFG_REGS		((GLOBAL_CFG_Type *) GCFG_BASE)
+
 /** @} *//* End of group MEC1501 */
 
 /** @} *//* End of group MCHP */
diff --git a/ext/hal/microchip/mec/mec1501/component/global_cfg.h b/ext/hal/microchip/mec/mec1501/component/global_cfg.h
new file mode 100644
index 00000000000..31b10ede409
--- /dev/null
+++ b/ext/hal/microchip/mec/mec1501/component/global_cfg.h
@@ -0,0 +1,158 @@
+/**
+ *
+ * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/** @file global_cfg.h
+ *MEC1501 Global Configuration Registers
+ */
+/** @defgroup MEC1501 Peripherals GlobalConfig
+ */
+
+#ifndef _GLOBAL_CFG_H
+#define _GLOBAL_CFG_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include "regaccess.h"
+
+/* ===================================================================*/
+/* ================	Global Config			============= */
+/* ===================================================================*/
+
+#define MCHP_GCFG_BASE_ADDR	0x400FFF00ul
+
+/*
+ * Device and Revision ID 32-bit register
+ * b[7:0] = Revision
+ * b[15:8] = Device Sub-ID
+ * b[31:16] = Device ID
+ * This register can be accesses as bytes or a single 32-bit read from
+ * the EC. Host access byte access via the Host visible configuration
+ * register space at 0x2E/0x2F(default).
+ */
+#define MCHP_GCFG_DEV_ID_REG32_OFS	0x1C
+#define MCHP_GCFG_DEV_ID_REG_MASK	0xFFFFFFFFul
+#define MCHP_GCFG_REV_ID_POS		0
+#define MCHP_GCFG_DID_REV_MASK0		0xFFul
+#define MCHP_GCFG_DID_REV_MASK		0xFFul
+#define MCHP_GCFG_DID_SUB_ID_POS	8
+#define MCHP_GCFG_DID_SUB_ID_MASK0	0xFFul
+#define MCHP_GCFG_DID_SUB_ID_MASK	(0xFFul << 8)
+#define MCHP_GCFG_DID_DEV_ID_POS	16
+#define MCHP_GCFG_DID_DEV_ID_MASK0	0xFFFFul
+#define MCHP_GCFG_DID_DEV_ID_MASK	(0xFFFFul << 16)
+
+/* Byte[0] at offset 0x1C is the 8-bit revision ID */
+#define MCHP_GCFG_REV_ID_REG_OFS	0x1C
+#define MCHP_GCFG_REV_A1		0x02
+#define MCHP_GCFG_REV_B0		0x03
+
+/* 
+ * Byte[1] at offset 0x1D is the 8-bit Sub-ID 
+ * bits[3:0] = package type
+ * bits[7:4] = chip family
+ */
+#define MCHP_GCFG_SUB_ID_OFS		0x1D
+#define MCHP_GCFG_SUB_ID_PKG_POS	0
+#define MCHP_GCFG_SUB_ID_PKG_MASK0	0x0F
+#define MCHP_GCFG_SUB_ID_PKG_MASK	0x0F
+#define MCHP_GCFG_SUB_ID_PKG_UNDEF	0x00
+#define MCHP_GCFG_SUB_ID_PKG_64_PIN	0x01
+#define MCHP_GCFG_SUB_ID_PKG_84_PIN	0x02
+#define MCHP_GCFG_SUB_ID_PKG_128_PIN	0x03
+#define MCHP_GCFG_SUB_ID_PKG_144_PIN	0x04
+/* chip family field */
+#define MCHP_GCFG_SUB_ID_FAM_POS	4
+#define MCHP_GCFG_SUB_ID_FAM_MASK0	0x0F
+#define MCHP_GCFG_SUB_ID_FAM_MASK	0xF0
+#define MCHP_GCFG_SUB_ID_FAM_UNDEF	0x00
+#define MCHP_GCFG_SUB_ID_FAM_MEC	0x01
+#define MCHP_GCFG_SUB_ID_FAM_2		0x02
+#define MCHP_GCFG_SUB_ID_FAM_3		0x03
+#define MCHP_GCFG_SUB_ID_FAM_4		0x04
+#define MCHP_GCFG_SUB_ID_FAM_5		0x05
+
+#define MCHP_GCFG_DEV_ID_LSB_OFS	0x1E
+#define MCHP_GCFG_DEV_ID_MSB_OFS	0x1F
+#define MCHP_GCFG_DEV_ID_15XX		0x0020
+#define MCHP_GCFG_DEV_ID_15XX_LSB	0x20
+#define MCHP_GCFG_DEV_ID_15XX_MSB	0x00
+
+/* Legacy Device ID value */
+#define MCHP_CCFG_LEGACY_DID_REG_OFS	0x20
+#define MCHP_GCFG_LEGACY_DEV_ID		0xFE
+
+/*
+ * Host access via configuration port (default I/O locations 0x2E/0x2F)
+ */
+#define MCHP_HOST_CFG_INDEX_IO_DFLT	0x2E
+#define MCHP_HOST_CFG_DATA_IO_DFLT	0x2F
+#define MCHP_HOST_CFG_UNLOCK	0x55
+#define MCHP_HOST_CFG_LOCK	0xAA
+/* 
+ * Logical Device Configuration Indices.
+ */
+#define MCHP_HOST_CFG_LDN_IDX		0x07
+#define MCHP_HOST_CFG_LD_ACTIVATE_IDX	0x30
+#define MCHP_HOST_CFG_LD_BASE_ADDR_IDX	0x34
+#define MCHP_HOST_CFG_LD_CFG_SEL_IDX	0xF0
+
+
+/* Read 32-bit Device, Sub, and Revision ID */
+#define MCHP_DEVICE_REV_ID() \
+	REG32(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_REG32_OFS)
+
+/* Read 16-bit Device ID */
+#define MCHP_DEVICE_ID() \
+	REG16(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_DEV_ID_LSB_OFS)
+
+/* Read 8-bit Sub ID */
+#define MCHP_DEV_SUB_ID() \
+	REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_SUB_ID_OFS)
+	
+/* Read 8-bit Revision ID */
+#define MCHP_REVISION_ID() \
+	REG8(MCHP_GCFG_BASE_ADDR + MCHP_GCFG_REV_ID_REG_OFS)
+
+/**
+  * @brief Glocal Configuration Registers (GLOBAL_CFG)
+  */
+typedef struct global_cfg_regs
+{
+	__IOM uint8_t  RSVD0[2];
+	__IOM uint8_t  TEST02;		/*!< (@ 0x0002) MCHP Test */
+	__IOM uint8_t  RSVD1[4];
+	__IOM uint8_t  LOG_DEV_NUM;	/*!< (@ 0x0007) Global Config Logical Device Number */
+	__IOM uint8_t  RSVD2[20];
+	__IOM uint32_t DEV_REV_ID;	/*!< (@ 0x001C) Device and revision ID */
+	__IOM uint8_t  LEGACY_DEV_ID;	/*!< (@ 0x0020) Legacy Device ID */
+	__IOM uint8_t  RSVD3[14];
+} GLOBAL_CFG_Type;
+
+#endif	/* #ifndef _GLOBAL_CFG_H */
+/* end global_cfg.h */
+/**   @}
+ */
diff --git a/ext/hal/microchip/mec/mec1501/component/ps2_ctrl.h b/ext/hal/microchip/mec/mec1501/component/ps2_ctrl.h
new file mode 100644
index 00000000000..5e292ef503b
--- /dev/null
+++ b/ext/hal/microchip/mec/mec1501/component/ps2_ctrl.h
@@ -0,0 +1,168 @@
+/**
+ *
+ * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/** @file ps2_ctrl.h
+ *MEC1501 PS/2 Controller Registers
+ */
+/** @defgroup MEC1501 Peripherals PS/2
+ */
+
+#ifndef _PS2_CTRL_H
+#define _PS2_CTRL_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include "regaccess.h"
+
+/* ===================================================================*/
+/* ================		PS2			============= */
+/* ===================================================================*/
+
+#define MCHP_PS2_MAX_INSTANCES	2u
+#define MCHP_PS2_SPACING	0x40ul
+#define MCHP_PS2_SPACING_PWROF2	6u
+
+#define MCHP_PS2_0_BASE_ADDR	0x40009000ul
+#define MCHP_PS2_1_BASE_ADDR	0x40009040ul
+
+/*
+ * PS2 interrupts
+ */
+#define MCHP_PS2_0_GIRQ			18u
+#define MCHP_PS2_1_GIRQ			18u
+#define MCHP_PS2_0_GIRQ_NVIC		10u
+#define MCHP_PS2_1_GIRQ_NVIC		10u
+#define MCHP_PS2_0_NVIC_DIRECT		100u
+#define MCHP_PS2_1_NVIC_DIRECT		101u
+
+#define MCHP_PS2_0_GIRQ_POS	10u
+#define MCHP_PS2_1_GIRQ_POS	11u
+
+#define MCHP_PS2_0_GIRQ_VAL	(1ul << 10)
+#define MCHP_PS2_1_GIRQ_VAL	(1ul << 11)
+
+/*
+ * PS2 TRX Buffer register
+ * Writes -> Transmit buffer
+ * Read <- Receive buffer
+ */
+#define MCHP_PS2_TRX_BUFF_REG_MASK	0xFFUL
+
+/*
+ * PS2 Control register
+ */
+#define MCHP_PS2_CTRL_REG_MASK		0x3FUL
+
+/* Select Transmit or Receive */
+#define MCHP_PS2_CTRL_TR_POS		0
+#define MCHP_PS2_CTRL_TR_RX		(0U << (MCHP_PS2_CTRL_TR_POS))
+#define MCHP_PS2_CTRL_TR_TX		(1U << (MCHP_PS2_CTRL_TR_POS))
+
+/* Enable PS2 state machine */
+#define MCHP_PS2_CTRL_EN_POS		1
+#define MCHP_PS2_CTRL_EN		(1U << (MCHP_PS2_CTRL_EN_POS))
+
+/* Protocol parity selection */
+#define MCHP_PS2_CTRL_PAR_POS		2
+#define MCHP_PS2_CTRL_PAR_MASK0		0x03U
+#define MCHP_PS2_CTRL_PAR_MASK		((MCHP_PS2_CTRL_PAR_MASK0) \
+						<< (MCHP_PS2_CTRL_PAR_POS))
+#define MCHP_PS2_CTRL_PAR_ODD		(0U << (MCHP_PS2_CTRL_PAR_POS))
+#define MCHP_PS2_CTRL_PAR_EVEN		(1U << (MCHP_PS2_CTRL_PAR_POS))
+#define MCHP_PS2_CTRL_PAR_IGNORE	(2U << (MCHP_PS2_CTRL_PAR_POS))
+#define MCHP_PS2_CTRL_PAR_RSVD		(3U << (MCHP_PS2_CTRL_PAR_POS))
+
+/* Protocol stop bit selection */
+#define MCHP_PS2_CTRL_STOP_POS		4
+#define MCHP_PS2_CTRL_STOP_MASK0	0x03U
+#define MCHP_PS2_CTRL_STOP_MASK		((MCHP_PS2_CTRL_STOP_MASK0) \
+						<< (MCHP_PS2_CTRL_STOP_POS))
+#define MCHP_PS2_CTRL_STOP_ACT_HI	(0U << (MCHP_PS2_CTRL_STOP_POS))
+#define MCHP_PS2_CTRL_STOP_ACT_LO	(1U << (MCHP_PS2_CTRL_STOP_POS))
+#define MCHP_PS2_CTRL_STOP_IGNORE	(2U << (MCHP_PS2_CTRL_STOP_POS))
+#define MCHP_PS2_CTRL_STOP_RSVD		(3U << (MCHP_PS2_CTRL_STOP_POS))
+
+/*
+ * PS2 Status register
+ */
+#define MCHP_PS2_STATUS_REG_MASK	0xFFUL
+#define MCHP_PS2_STATUS_RW1C_MASK	0xAEUL
+#define MCHP_PS2_STATUS_RO_MASK		0x51UL
+/* RX Data Ready(Read-Only) */
+#define MCHP_PS2_STATUS_RXD_RDY_POS	0
+#define MCHP_PS2_STATUS_RXD_RDY		(1U << (MCHP_PS2_STATUS_RXD_RDY_POS))
+/* RX Timeout(R/W1C) */
+#define MCHP_PS2_STATUS_RX_TMOUT_POS	1
+#define MCHP_PS2_STATUS_RX_TMOUT	(1U << (MCHP_PS2_STATUS_RX_TMOUT_POS))
+/* Parity Error(R/W1C) */
+#define MCHP_PS2_STATUS_PE_POS		2
+#define MCHP_PS2_STATUS_PE		(1U << (MCHP_PS2_STATUS_PE_POS))
+/* Framing Error(R/W1C) */
+#define MCHP_PS2_STATUS_FE_POS		3
+#define MCHP_PS2_STATUS_FE		(1U << (MCHP_PS2_STATUS_FE_POS))
+/* Transmitter is Idle(Read-Only) */
+#define MCHP_PS2_STATUS_TX_IDLE_POS	4
+#define MCHP_PS2_STATUS_TX_IDLE		(1U << (MCHP_PS2_STATUS_TX_IDLE_POS))
+/* Transmitter timeout(R/W1C) */
+#define MCHP_PS2_STATUS_TX_TMOUT_POS	5
+#define MCHP_PS2_STATUS_TX_TMOUT	(1U << (MCHP_PS2_STATUS_TX_TMOUT_POS))
+/* RX is Busy(Read-Only) */
+#define MCHP_PS2_STATUS_RX_BUSY_POS	6
+#define MCHP_PS2_STATUS_RX_BUSY		(1U << (MCHP_PS2_STATUS_RX_BUSY_POS))
+/* Transmitter start timeout(R/W1C) */
+#define MCHP_PS2_STATUS_TX_ST_TMOUT_POS	7
+#define MCHP_PS2_STATUS_TX_ST_TMOUT	(1U << (MCHP_PS2_STATUS_TX_ST_TMOUT_POS))
+
+/*
+ * PS2 Protocol bit positions
+ */
+#define MCHP_PS2_PROT_START_BIT_POS	1
+#define MCHP_PS2_PROT_DATA_BIT0_POS	2
+#define MCHP_PS2_PROT_DATA_BIT1_POS	3
+#define MCHP_PS2_PROT_DATA_BIT2_POS	4
+#define MCHP_PS2_PROT_DATA_BIT3_POS	5
+#define MCHP_PS2_PROT_DATA_BIT4_POS	6
+#define MCHP_PS2_PROT_DATA_BIT5_POS	7
+#define MCHP_PS2_PROT_DATA_BIT6_POS	8
+#define MCHP_PS2_PROT_DATA_BIT7_POS	9
+#define MCHP_PS2_PROT_PARITY_POS	10
+#define MCHP_PS2_PROT_STOP_BIT_POS	11
+
+/**
+  * @brief PS/2 Controller Registers (PS2)
+  */
+typedef struct ps2_regs
+{
+	__IOM uint32_t TRX_BUFF;	/*!< (@ 0x0000) PS/2 Transmit buffer(WO), Receive buffer(RO) */
+	__IOM uint32_t CTRL;		/*!< (@ 0x0004) PS/2 Control */
+	__IOM uint32_t STATUS;		/*!< (@ 0x0008) PS/2 Status */
+} PS2_Type;
+
+#endif	/* #ifndef _PS2_CTRL_H */
+/* end ps2_ctrl.h */
+/**   @}
+ */