michaelh/zephyr
1
0
Fork 0
Code Releases Activity

x86: remove HAS_DTS checking

Browse source 
All X86 boards are now DTS enabled.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2017-12-15 16:43:33 -05:00 • committed by Kumar Gala
commit b8ea7c889d
5 changed files with 6 additions and 116 deletions
Download patch file Download diff file Expand all files Collapse all files

16
arch/x86/core/Kconfig
View file

@ -48,22 +48,6 @@ config MAX_IRQ_LINES
to program to the PIC the association between vectors and to program to the PIC the association between vectors and
interrupts. interrupts.
if !HAS_DTS
config PHYS_LOAD_ADDR
hex "Physical load address"
# Default value must be supplied by platform
help
This option specifies the physical address where the kernel is loaded.
endif
if !HAS_DTS
config PHYS_RAM_ADDR
hex "Physical RAM address"
# Default value must be supplied by platform
help
This option specifies the physical RAM address of the selected SoC.
endif
config RAM_SIZE config RAM_SIZE
int "Amount of RAM given to the kernel (in kB)" int "Amount of RAM given to the kernel (in kB)"
help help

32
arch/x86/soc/atom/Kconfig.defconfig
View file

@ -11,14 +11,6 @@ if SOC_ATOM
config SOC config SOC
default atom default atom
if !HAS_DTS
config PHYS_LOAD_ADDR
default 0x00100000
config PHYS_RAM_ADDR
default 0x00400000
endif
config RAM_SIZE config RAM_SIZE
default 128 if XIP default 128 if XIP
default 256 default 256
@ -43,16 +35,9 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
if !HAS_DTS
config UART_NS16550_PORT_0_NAME
default "UART_0"
endif
config UART_NS16550_PORT_0_IRQ_PRI config UART_NS16550_PORT_0_IRQ_PRI
default 3 default 3
if !HAS_DTS
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
endif
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
@ -63,16 +48,9 @@ config UART_NS16550_PORT_1
if UART_NS16550_PORT_1 if UART_NS16550_PORT_1
if !HAS_DTS
config UART_NS16550_PORT_1_NAME
default "UART_1"
endif
config UART_NS16550_PORT_1_IRQ_PRI config UART_NS16550_PORT_1_IRQ_PRI
default 3 default 3
if !HAS_DTS
config UART_NS16550_PORT_1_BAUD_RATE
default 115200
endif
config UART_NS16550_PORT_1_OPTIONS config UART_NS16550_PORT_1_OPTIONS
default 0 default 0
@ -82,12 +60,6 @@ endif # UART_NS16550
if BT_UART if BT_UART
if !HAS_DTS
config BT_UART_ON_DEV_NAME
default "UART_1"
endif
if UART_PIPE if UART_PIPE
config UART_PIPE_ON_DEV_NAME config UART_PIPE_ON_DEV_NAME

13
arch/x86/soc/intel_quark/quark_d2000/Kconfig.defconfig.series
View file

@ -19,12 +19,6 @@ config TOOLCHAIN_VARIANT
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32000000 default 32000000
if !HAS_DTS
config PHYS_LOAD_ADDR
default 0x00180000 if XIP
default 0x00280000 if !XIP
endif
config RAM_SIZE config RAM_SIZE
default 8 default 8
@ -43,13 +37,6 @@ config LOAPIC_TIMER_IRQ
config LOAPIC_TIMER_IRQ_PRIORITY config LOAPIC_TIMER_IRQ_PRIORITY
default 2 default 2
if !HAS_DTS
config PHYS_RAM_ADDR
default 0x00280000
help
This option specifies the physical SRAM address of this Soc.
endif
config QMSI config QMSI
def_bool y def_bool y

28
arch/x86/soc/intel_quark/quark_se/Kconfig.defconfig.series
View file

@ -19,16 +19,6 @@ config TOOLCHAIN_VARIANT
default "iamcu" if X86_IAMCU default "iamcu" if X86_IAMCU
default "" if !X86_IAMCU default "" if !X86_IAMCU
if !HAS_DTS
config PHYS_RAM_ADDR
default 0xA8006400
endif
if !HAS_DTS
config PHYS_LOAD_ADDR
default 0x40030000 if XIP
endif
config RAM_SIZE config RAM_SIZE
default 52 default 52
@ -201,19 +191,9 @@ endif # RTC
if BT_H4 if BT_H4
if !HAS_DTS
config BT_UART_ON_DEV_NAME
default UART_QMSI_0_NAME
endif
config UART_QMSI_0 config UART_QMSI_0
def_bool y def_bool y
if !HAS_DTS
config UART_QMSI_0_BAUDRATE
default 1000000
endif
config UART_QMSI_0_HW_FC config UART_QMSI_0_HW_FC
def_bool y def_bool y
@ -240,14 +220,6 @@ endif # UART_QMSI_1
endif # UART_QMSI endif # UART_QMSI
if UART_CONSOLE && !HAS_DTS
config UART_CONSOLE_ON_DEV_NAME
default "UART_1" if USB_UART_CONSOLE = n
default "CDC_ACM" if USB_UART_CONSOLE
endif
if SOC_FLASH_QMSI if SOC_FLASH_QMSI
config SOC_FLASH_QMSI_SYS_SIZE config SOC_FLASH_QMSI_SYS_SIZE
default 0x60000 default 0x60000

33
arch/x86/soc/intel_quark/quark_x1000/Kconfig.defconfig.series
View file

@ -12,14 +12,6 @@ if SOC_SERIES_QUARK_X1000
config SOC_SERIES config SOC_SERIES
default quark_x1000 default quark_x1000
if !HAS_DTS
config PHYS_LOAD_ADDR
default 0x00100000
config PHYS_RAM_ADDR
default 0x00400000
endif
config RAM_SIZE config RAM_SIZE
default 32768 default 32768
@ -202,18 +194,12 @@ config UART_NS16550_PORT_0
if UART_NS16550_PORT_0 if UART_NS16550_PORT_0
if !HAS_DTS
config UART_NS16550_PORT_0_NAME
default "UART_0"
endif
config UART_NS16550_PORT_0_IRQ_PRI config UART_NS16550_PORT_0_IRQ_PRI
default 0 default 0
if !HAS_DTS
config UART_NS16550_PORT_0_BAUD_RATE
default 115200
endif
config UART_NS16550_PORT_0_OPTIONS config UART_NS16550_PORT_0_OPTIONS
default 0 default 0
config UART_NS16550_PORT_0_PCI config UART_NS16550_PORT_0_PCI
def_bool y if UART_NS16550_PCI def_bool y if UART_NS16550_PCI
@ -224,18 +210,12 @@ config UART_NS16550_PORT_1
if UART_NS16550_PORT_1 if UART_NS16550_PORT_1
if !HAS_DTS
config UART_NS16550_PORT_1_NAME
default "UART_1"
endif
config UART_NS16550_PORT_1_IRQ_PRI config UART_NS16550_PORT_1_IRQ_PRI
default 3 default 3
if !HAS_DTS
config UART_NS16550_PORT_1_BAUD_RATE
default 115200
endif
config UART_NS16550_PORT_1_OPTIONS config UART_NS16550_PORT_1_OPTIONS
default 0 default 0
config UART_NS16550_PORT_1_PCI config UART_NS16550_PORT_1_PCI
def_bool y if UART_NS16550_PCI def_bool y if UART_NS16550_PCI
@ -270,11 +250,6 @@ config PINMUX_INIT_PRIORITY
if UART_CONSOLE if UART_CONSOLE
if !HAS_DTS
config UART_CONSOLE_ON_DEV_NAME
default "UART_1"
endif
endif endif
if BT_UART if BT_UART