From b8604024f7ceadafd5778e78640102023b6ebc33 Mon Sep 17 00:00:00 2001
From: Konstantinos Papadopoulos <kostas.papadopulos@gmail.com>
Date: Mon, 4 Apr 2022 20:33:58 +0300
Subject: [PATCH] drivers: display: stm32_ltdc temporary patch for LTDC clock

LTDC clock on F4/F7 series, is generated from PLLSAI which yet is not
implemented into Zephyr.

Signed-off-by: Konstantinos Papadopoulos <kostas.papadopulos@gmail.com>
---
 drivers/display/display_stm32_ltdc.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
index dd4232a57d0..6c2a0172050 100644
--- a/drivers/display/display_stm32_ltdc.c
+++ b/drivers/display/display_stm32_ltdc.c
@@ -9,6 +9,7 @@
 #include <string.h>
 #include <device.h>
 #include <devicetree.h>
+#include <stm32_ll_rcc.h>
 #include <drivers/display.h>
 #include <drivers/gpio.h>
 #include <drivers/pinctrl.h>
@@ -248,6 +249,32 @@ static int stm32_ltdc_init(const struct device *dev)
 		return err;
 	}
 
+#if defined(CONFIG_SOC_SERIES_STM32F4X)
+	LL_RCC_PLLSAI_Disable();
+	LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
+					LL_RCC_PLLSAIM_DIV_8,
+					192,
+					LL_RCC_PLLSAIR_DIV_4,
+					LL_RCC_PLLSAIDIVR_DIV_8);
+
+	LL_RCC_PLLSAI_Enable();
+	while (LL_RCC_PLLSAI_IsReady() != 1) {
+	}
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32F7X)
+	LL_RCC_PLLSAI_Disable();
+	LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
+					LL_RCC_PLLM_DIV_8,
+					192,
+					LL_RCC_PLLSAIR_DIV_4,
+					LL_RCC_PLLSAIDIVR_DIV_8);
+
+	LL_RCC_PLLSAI_Enable();
+	while (LL_RCC_PLLSAI_IsReady() != 1) {
+	}
+#endif
+
 	/* reset LTDC peripheral */
 	__HAL_RCC_LTDC_FORCE_RESET();
 	__HAL_RCC_LTDC_RELEASE_RESET();