x86: consolidate x86_64 architecture, SoC and boards
There are two set of code supporting x86_64: x86_64 using x32 ABI, and x86 long mode, and this consolidates both into one x86_64 architecture and SoC supporting truly 64-bit mode. () Removes the x86_64:x32 architecture and SoC, and replaces them with the existing x86 long mode arch and SoC. () Replace qemu_x86_64 with qemu_x86_long as qemu_x86_64. () Updates samples and tests to remove reference to qemu_x86_long. () Renames CONFIG_X86_LONGMODE to CONFIG_X86_64. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
421935efa5
commit
b7eb04b300
103 changed files with 105 additions and 3102 deletions
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@ -13,8 +13,6 @@
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#if defined(CONFIG_X86)
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#include <arch/x86/arch.h>
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#elif defined(CONFIG_X86_64)
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#include <arch/x86_64/arch.h>
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#elif defined(CONFIG_ARM)
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#include <arch/arm/arch.h>
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#elif defined(CONFIG_ARC)
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@ -9,7 +9,7 @@
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#ifndef ZEPHYR_INCLUDE_ARCH_SYSCALL_H_
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#define ZEPHYR_INCLUDE_ARCH_SYSCALL_H_
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#if defined(CONFIG_X86) && !defined(CONFIG_X86_LONGMODE)
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#if defined(CONFIG_X86) && !defined(CONFIG_X86_64)
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#include <arch/x86/ia32/syscall.h>
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#elif defined(CONFIG_ARM)
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#include <arch/arm/syscall.h>
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@ -198,7 +198,7 @@ extern unsigned char _irq_to_interrupt_vector[];
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#endif /* _ASMLANGUAGE */
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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#include <arch/x86/intel64/arch.h>
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#else
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#include <arch/x86/ia32/arch.h>
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@ -38,7 +38,7 @@
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#define Z_X86_MMU_G BIT64(8) /** Global */
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#define Z_X86_MMU_XD BIT64(63) /** Execute Disable */
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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#define Z_X86_MMU_PROT_KEY_MASK 0x7800000000000000ULL
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#endif
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@ -54,11 +54,11 @@
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* reserved or ignored regions immediately above it, into a single area.
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* This will work as expected if valid memory addresses are written.
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*/
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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#define Z_X86_MMU_PML4E_PDPT_MASK 0x7FFFFFFFFFFFF000ULL
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#endif
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#define Z_X86_MMU_PDPTE_PD_MASK 0x7FFFFFFFFFFFF000ULL
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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#define Z_X86_MMU_PDPTE_1G_MASK 0x07FFFFFFC0000000ULL
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#endif
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#define Z_X86_MMU_PDE_PT_MASK 0x7FFFFFFFFFFFF000ULL
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@ -163,7 +163,7 @@ struct mmu_region {
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#define MMU_BOOT_REGION(addr, region_size, permission_flags) \
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Z_MMU_BOOT_REGION(__COUNTER__, addr, region_size, permission_flags)
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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#define Z_X86_NUM_PML4_ENTRIES 512U
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#define Z_X86_NUM_PDPT_ENTRIES 512U
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#else
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@ -179,7 +179,7 @@ struct mmu_region {
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typedef u64_t k_mem_partition_attr_t;
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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struct x86_mmu_pml4 {
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u64_t entry[Z_X86_NUM_PML4_ENTRIES];
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};
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@ -198,7 +198,7 @@ struct x86_mmu_pt {
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};
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struct x86_page_tables {
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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struct x86_mmu_pml4 pml4;
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#else
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struct x86_mmu_pdpt pdpt;
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@ -208,7 +208,7 @@ struct x86_page_tables {
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/*
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* Inline functions for getting the next linked structure
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*/
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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static inline u64_t *z_x86_pml4_get_pml4e(struct x86_mmu_pml4 *pml4,
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uintptr_t addr)
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{
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@ -237,7 +237,7 @@ static inline struct x86_mmu_pd *z_x86_pdpte_get_pd(u64_t pdpte)
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{
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uintptr_t addr = pdpte & Z_X86_MMU_PDPTE_PD_MASK;
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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__ASSERT((pdpte & Z_X86_MMU_PS) == 0, "PDPT is for 1GB page");
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#endif
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return (struct x86_mmu_pd *)addr;
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@ -270,7 +270,7 @@ static inline u64_t *z_x86_pt_get_pte(struct x86_mmu_pt *pt, uintptr_t addr)
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* Inline functions for obtaining page table structures from the top-level
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*/
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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static inline struct x86_mmu_pml4 *
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z_x86_get_pml4(struct x86_page_tables *ptables)
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{
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@ -296,7 +296,7 @@ z_x86_get_pdpt(struct x86_page_tables *ptables, uintptr_t addr)
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return &ptables->pdpt;
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}
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#endif /* CONFIG_X86_LONGMODE */
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#endif /* CONFIG_X86_64 */
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static inline u64_t *z_x86_get_pdpte(struct x86_page_tables *ptables,
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uintptr_t addr)
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@ -46,7 +46,7 @@ static inline void z_x86_msr_write(unsigned int msr, u64_t data)
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__asm__ volatile ("wrmsr" : : "c"(msr), "a"(low), "d"(high));
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}
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#ifdef CONFIG_X86_LONGMODE
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#ifdef CONFIG_X86_64
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static inline u64_t z_x86_msr_read(unsigned int msr)
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{
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@ -1,82 +0,0 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _X86_64_ARCH_H
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#define _X86_64_ARCH_H
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#include <arch/common/sys_io.h>
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#include <arch/common/ffs.h>
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#define STACK_ALIGN 8
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#define DT_INST_0_INTEL_HPET_BASE_ADDRESS 0xFED00000U
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#define DT_INST_0_INTEL_HPET_IRQ_0 2
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#define DT_INST_0_INTEL_HPET_IRQ_0_PRIORITY 4
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typedef struct z_arch_esf_t z_arch_esf_t;
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static inline u32_t z_arch_k_cycle_get_32(void)
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{
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#ifdef CONFIG_HPET_TIMER
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extern u32_t z_timer_cycle_get_32(void);
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return z_timer_cycle_get_32();
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#else
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return (u32_t)z_arch_k_cycle_get_64();
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#endif
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}
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/* Not a standard Zephyr function, but probably will be */
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static inline unsigned long long z_arch_k_cycle_get_64(void)
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{
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unsigned int hi, lo;
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__asm__ volatile("rdtsc" : "=d"(hi), "=a"(lo));
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return (((unsigned long long)hi) << 32) | lo;
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}
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static inline unsigned int z_arch_irq_lock(void)
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{
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unsigned long long key;
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__asm__ volatile("pushfq; cli; popq %0" : "=r"(key));
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return (int)key;
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}
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static inline void z_arch_irq_unlock(unsigned int key)
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{
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if (key & 0x200) {
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__asm__ volatile("sti");
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}
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}
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/**
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* Returns true if interrupts were unlocked prior to the
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* z_arch_irq_lock() call that produced the key argument.
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*/
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static inline bool z_arch_irq_unlocked(unsigned int key)
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{
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return (key & 0x200) != 0;
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}
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void z_arch_irq_enable(unsigned int irq);
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void z_arch_irq_disable(unsigned int irq);
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#define Z_ARCH_IRQ_CONNECT(irq, pri, isr, arg, flags) \
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z_arch_irq_connect_dynamic(irq, pri, isr, arg, flags)
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extern int x86_64_except_reason;
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/* Vector 5 is the "bounds" exception which is otherwise vestigial
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* (BOUND is an illegal instruction in long mode)
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*/
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#define Z_ARCH_EXCEPT(reason) do { \
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x86_64_except_reason = reason; \
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__asm__ volatile("int $5"); \
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} while (false)
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#endif /* _X86_64_ARCH_H */
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