dts: riscv32: riscv32-qemu: Add device tree support
add device tree support for riscv32-qemu Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This commit is contained in:
parent
268c0e3310
commit
b7c4c0302c
8 changed files with 102 additions and 13 deletions
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@ -20,18 +20,6 @@ config NUM_IRQS
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int
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default 32
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config RISCV_ROM_BASE_ADDR
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hex
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default 0x00001000
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config RISCV_ROM_SIZE
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hex
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default 0x100000
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config RISCV_RAM_BASE_ADDR
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hex
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default 0x80000000
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config RISCV_RAM_SIZE_MB
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int
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default 32
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5
arch/riscv32/soc/riscv-privilege/riscv32-qemu/dts.fixup
Normal file
5
arch/riscv32/soc/riscv-privilege/riscv32-qemu/dts.fixup
Normal file
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@ -0,0 +1,5 @@
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#define CONFIG_RISCV_RAM_BASE_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CONFIG_RISCV_ROM_BASE_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define CONFIG_RISCV_ROM_SIZE (CONFIG_FLASH_SIZE *1024)
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@ -7,5 +7,5 @@
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/**
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* @brief Linker script for riscv32-qemu
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*/
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#include <generated_dts_board.h>
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#include <arch/riscv32/common/linker.ld>
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@ -3,3 +3,4 @@ config BOARD_QEMU_RISCV32
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bool "QEMU RISCV32 target"
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depends on SOC_RISCV32_QEMU
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select QEMU_TARGET
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select HAS_DTS
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23
boards/riscv32/qemu_riscv32/qemu_riscv32.dts
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23
boards/riscv32/qemu_riscv32/qemu_riscv32.dts
Normal file
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@ -0,0 +1,23 @@
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/dts-v1/;
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#include <riscv32-qemu.dtsi>
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/ {
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model = "qemu_riscv32";
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compatible = "qemu,riscv32";
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aliases {
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uart_0 = &uart0;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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};
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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};
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30
dts/bindings/serial/riscv,qemu-uart.yaml
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30
dts/bindings/serial/riscv,qemu-uart.yaml
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@ -0,0 +1,30 @@
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---
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title: RISCV QEMU UART
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id: riscv,qemu-uart
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version: 0.1
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description: >
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This binding gives a base representation of the RISCV QEMU UART
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inherits:
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!include uart.yaml
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "riscv,qemu-uart"
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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...
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41
dts/riscv32/riscv32-qemu.dtsi
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41
dts/riscv32/riscv32-qemu.dtsi
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@ -0,0 +1,41 @@
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#include "skeleton.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qemu,riscv32";
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reg = <0>;
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};
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};
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flash0: flash@1000 {
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reg = <0x1000 0x100000>;
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};
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sram0: memory@80000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x80000000 0x2000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@40002000 {
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compatible = "riscv,qemu-uart";
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reg = <0x40002000 0x400>;
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label = "uart0";
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status = "disabled";
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};
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};
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};
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@ -20,6 +20,7 @@
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#include <irq.h>
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#include <sw_isr_table.h>
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#include <soc.h>
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#include <generated_dts_board.h>
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#ifdef __cplusplus
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extern "C" {
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