dts: riscv32: riscv32-qemu: Add device tree support

add device tree support for riscv32-qemu

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>

arch/riscv32/soc/riscv-privilege/riscv32-qemu/Kconfig.defconfig.series

@@ -20,18 +20,6 @@ config NUM_IRQS
 	int
 	default 32
 
-config RISCV_ROM_BASE_ADDR
-	hex
-	default 0x00001000
-
-config RISCV_ROM_SIZE
-	hex
-	default 0x100000
-
-config RISCV_RAM_BASE_ADDR
-	hex
-	default	0x80000000
-
 config RISCV_RAM_SIZE_MB
 	int
 	default 32

arch/riscv32/soc/riscv-privilege/riscv32-qemu/dts.fixup

@@ -0,0 +1,5 @@
+#define CONFIG_RISCV_RAM_BASE_ADDR		CONFIG_SRAM_BASE_ADDRESS
+
+#define CONFIG_RISCV_ROM_BASE_ADDR		CONFIG_FLASH_BASE_ADDRESS
+
+#define CONFIG_RISCV_ROM_SIZE			(CONFIG_FLASH_SIZE *1024)

arch/riscv32/soc/riscv-privilege/riscv32-qemu/linker.ld

@@ -7,5 +7,5 @@
 /**
  * @brief Linker script for riscv32-qemu
  */
-
+#include <generated_dts_board.h>
 #include <arch/riscv32/common/linker.ld>

boards/riscv32/qemu_riscv32/Kconfig.board

@@ -3,3 +3,4 @@ config BOARD_QEMU_RISCV32
 	bool "QEMU RISCV32 target"
 	depends on SOC_RISCV32_QEMU
 	select QEMU_TARGET
+	select HAS_DTS

boards/riscv32/qemu_riscv32/qemu_riscv32.dts

@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include <riscv32-qemu.dtsi>
+
+/ {
+	model = "qemu_riscv32";
+	compatible = "qemu,riscv32";
+
+	aliases {
+		uart_0 = &uart0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+	};
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};

dts/bindings/serial/riscv,qemu-uart.yaml

@@ -0,0 +1,30 @@
+---
+title: RISCV QEMU UART
+id: riscv,qemu-uart
+version: 0.1
+
+description: >
+    This binding gives a base representation of the RISCV QEMU UART
+
+inherits:
+    !include uart.yaml
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "riscv,qemu-uart"
+
+    reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+    interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+...

dts/riscv32/riscv32-qemu.dtsi

@@ -0,0 +1,41 @@
+#include "skeleton.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "qemu,riscv32";
+			reg = <0>;
+		};
+
+	};
+
+	flash0: flash@1000 {
+		reg = <0x1000 0x100000>;
+	};
+
+	sram0: memory@80000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x80000000 0x2000000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0: uart@40002000 {
+			compatible = "riscv,qemu-uart";
+			reg = <0x40002000 0x400>;
+			label = "uart0";
+
+			status = "disabled";
+		};
+
+	};
+};

include/arch/riscv32/arch.h

@@ -20,6 +20,7 @@
 #include <irq.h>
 #include <sw_isr_table.h>
 #include <soc.h>
+#include <generated_dts_board.h>
 
 #ifdef __cplusplus
 extern "C" {