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soc: riscv: neorv32: reorganize SoC folder

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Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-01-03 15:50:51 +01:00 • committed by Carles Cufí
commit b7b19b8b05
11 changed files with 31 additions and 38 deletions
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2
boards/riscv/neorv32/Kconfig.board
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@ -3,4 +3,4 @@
config BOARD_NEORV32 config BOARD_NEORV32
bool "NEORV32 Processor (SoC)" bool "NEORV32 Processor (SoC)"
depends on SOC_SERIES_NEORV32 depends on SOC_NEORV32

2
boards/riscv/neorv32/neorv32_defconfig
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@ -1,7 +1,7 @@
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk> # Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_NEORV32=y CONFIG_SOC_NEORV32=y
CONFIG_SOC_NEORV32_ISA_C=y CONFIG_SOC_NEORV32_ISA_C=y
CONFIG_BOARD_NEORV32=y CONFIG_BOARD_NEORV32=y
CONFIG_SERIAL=y CONFIG_SERIAL=y

0
soc/riscv/riscv-privileged/neorv32/CMakeLists.txt → soc/riscv/neorv32/CMakeLists.txt
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6
soc/riscv/riscv-privileged/neorv32/Kconfig.defconfig.series → soc/riscv/neorv32/Kconfig.defconfig
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@ -1,9 +1,9 @@
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk> # Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NEORV32 if SOC_NEORV32
config SOC_SERIES config SOC
default "neorv32" default "neorv32"
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
@ -29,4 +29,4 @@ config ENTROPY_INIT_PRIORITY
default 55 default 55
depends on ENTROPY_GENERATOR depends on ENTROPY_GENERATOR
endif # SOC_SERIES_NEORV32 endif # SOC_NEORV32

27
soc/riscv/riscv-privileged/neorv32/Kconfig.series → soc/riscv/neorv32/Kconfig.soc
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@ -1,7 +1,7 @@
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk> # Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NEORV32 config SOC_NEORV32
bool "NEORV32 Processor" bool "NEORV32 Processor"
select RISCV select RISCV
select RISCV_ISA_RV32I select RISCV_ISA_RV32I
@ -10,6 +10,7 @@ config SOC_SERIES_NEORV32
select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED select RISCV_PRIVILEGED
select RISCV_PRIVILEGED_STANDALONE
help help
Enable support for the NEORV32 Processor (SoC). Enable support for the NEORV32 Processor (SoC).
@ -24,3 +25,27 @@ config SOC_SERIES_NEORV32
- E (Embedded, only 16 integer registers) - E (Embedded, only 16 integer registers)
- Zbb (Basic Bit Manipulation) - Zbb (Basic Bit Manipulation)
- Zfinx (Floating Point in Integer Registers) - Zfinx (Floating Point in Integer Registers)
if SOC_NEORV32
config SOC_NEORV32_V1_8_6
bool "v1.8.6"
# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
select ATOMIC_OPERATIONS_C
config SOC_NEORV32_VERSION
hex
default 0x01080600 if SOC_NEORV32_V1_8_6
help
The targeted NEORV32 version as BCD-coded number. The format is
identical to that of the NEORV32 Machine implementation ID (mimpid)
register.
config SOC_NEORV32_ISA_C
bool "RISC-V ISA Extension \"C\""
select RISCV_ISA_EXT_C
help
Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
"C" extension (Compressed Instructions).
endif # SOC_NEORV32

0
soc/riscv/riscv-privileged/neorv32/linker.ld → soc/riscv/neorv32/linker.ld
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0
soc/riscv/riscv-privileged/neorv32/reset.S → soc/riscv/neorv32/reset.S
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0
soc/riscv/riscv-privileged/neorv32/soc.c → soc/riscv/neorv32/soc.c
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0
soc/riscv/riscv-privileged/neorv32/soc.h → soc/riscv/neorv32/soc.h
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0
soc/riscv/riscv-privileged/neorv32/soc_irq.S → soc/riscv/neorv32/soc_irq.S
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32
soc/riscv/riscv-privileged/neorv32/Kconfig.soc
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@ -1,32 +0,0 @@
# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
choice
prompt "NEORV32 Version"
depends on SOC_SERIES_NEORV32
config SOC_NEORV32_V1_8_6
bool "v1.8.6"
# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
select ATOMIC_OPERATIONS_C
endchoice
if SOC_SERIES_NEORV32
config SOC_NEORV32_VERSION
hex
default 0x01080600 if SOC_NEORV32_V1_8_6
help
The targeted NEORV32 version as BCD-coded number. The format is
identical to that of the NEORV32 Machine implementation ID (mimpid)
register.
config SOC_NEORV32_ISA_C
bool "RISC-V ISA Extension \"C\""
select RISCV_ISA_EXT_C
help
Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
"C" extension (Compressed Instructions).
endif # SOC_SERIES_NEORV32