michaelh/zephyr
1
0
Fork 0
Code Releases Activity

xtensa: optionally build reset vector code

Browse source 
In real-world use-cases this isn't always needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2017-05-11 09:46:08 -07:00 • committed by Anas Nashif
commit b7aa6b7bd0
2 changed files with 10 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

9
arch/xtensa/Kconfig
View file

@ -68,6 +68,15 @@ config SW_ISR_TABLE_DYNAMIC
SRAM so that it is writable. This has the side-effect of removing SRAM so that it is writable. This has the side-effect of removing
write-protection on the ISR table. write-protection on the ISR table.
config XTENSA_RESET_VECTOR
bool
prompt "Build reset vector code"
default y
help
This option controls whether the initial reset vector code is built.
This is always needed for the simulator. Real boards may already
implement this in boot ROM.
menu "Specific core configuration" menu "Specific core configuration"
config IRQ_OFFLOAD_INTNUM config IRQ_OFFLOAD_INTNUM

2
arch/xtensa/core/startup/Makefile
View file

@ -1,2 +1,2 @@
asflags-y := -c -xassembler-with-cpp $(XTENSA_INCLUDE) $(flagBoardType) -mtext-section-literals -mlongcalls asflags-y := -c -xassembler-with-cpp $(XTENSA_INCLUDE) $(flagBoardType) -mtext-section-literals -mlongcalls
obj-y = reset-vector.o obj-$(CONFIG_XTENSA_RESET_VECTOR) = reset-vector.o