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intel_adsp: ace20_lnl: Add I2S clock source configuration

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Add I2CLCTL_MLCS programming in SSP driver.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit is contained in:
Jaroslaw Stelter 2023-02-27 13:03:03 +01:00 • committed by Anas Nashif
commit b75b4153d6
3 changed files with 11 additions and 8 deletions
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9
drivers/dai/intel/ssp/ssp.c
View file

@ -30,6 +30,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#define dai_ip_base(dai) dai->plat_data.ip_base
#define dai_shim_base(dai) dai->plat_data.shim_base
#define dai_hdamlssp_base(dai) dai->plat_data.hdamlssp_base
#define dai_i2svss_base(dai) dai->plat_data.i2svss_base
#define DAI_DIR_PLAYBACK 0
#define DAI_DIR_CAPTURE 1
@ -1708,9 +1709,15 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
#ifdef CONFIG_SOC_SERIES_INTEL_ACE
link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
#if CONFIG_SOC_INTEL_ACE15_MTPM
sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) |
I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
I2SLCTL_OFFSET);
#elif CONFIG_SOC_INTEL_ACE20_LNL
sys_write32(sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) |
I2CLCTL_MLCS(link->clock_source), dai_i2svss_base(dp) +
I2SLCTL_OFFSET);
#endif
LOG_INF("%s link clock_source %u", __func__, link->clock_source);
#endif
break;
@ -2256,6 +2263,8 @@ static const char irq_name_level5_z[] = "level5";
.shim_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(shim), 0), \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(hdamlssp)), \
(.hdamlssp_base = DT_REG_ADDR(DT_NODELABEL(hdamlssp)),))\
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(i2svss)), \
(.i2svss_base = DT_REG_ADDR(DT_NODELABEL(i2svss)),))\
.irq = n, \
.irq_name = irq_name_level5_z, \
.fifo[DAI_DIR_PLAYBACK].offset = \

3
drivers/dai/intel/ssp/ssp.h
View file

@ -221,7 +221,6 @@
#ifdef CONFIG_SOC_INTEL_ACE15_MTPM
#define I2SLCTL_SPA(x) BIT(0 + x)
#define I2SLCTL_CPA(x) BIT(8 + x)
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x)
#else /* CONFIG_SOC_INTEL_ACE20_LNL */
#define I2SLCTL_OFLEN BIT(4)
#define I2SLCTL_SPA(x) BIT(16 + x)
@ -230,6 +229,7 @@
#define PCMS1CM_OFFSET 0x1A
#endif /* CONFIG_SOC_INTEL_ACE15_MTPM */
#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x)
#define SHIM_CLKCTL 0x78
#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x)
#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x)
@ -319,6 +319,7 @@ struct dai_intel_ssp_plat_data {
uint32_t shim_base;
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
uint32_t hdamlssp_base;
uint32_t i2svss_base;
#endif
int irq;
const char *irq_name;

7
dts/bindings/i2s/intel,ssp-dai.yaml
View file

@ -24,12 +24,5 @@ properties:
dma-names:
required: true
shim2:
type: array
description: |
Intel HD Audio Multiple Links Capability Structure
for I2S / PCM Link.
i2svss:
type: array