From b7433fd297848c4d56d60254b5cd88c7b2b4babe Mon Sep 17 00:00:00 2001
From: Aaron Ye <aye@ambiq.com>
Date: Mon, 25 Sep 2023 12:08:24 +0800
Subject: [PATCH] dts: arm: ambiq: Add IOM instances to Apollo4 Blue Plus SoC.

This commit instantiates the IOM peripherals.
IOM can be configured to SPI or I2C master.

Signed-off-by: Aaron Ye <aye@ambiq.com>
---
 dts/arm/ambiq/ambiq_apollo4p_blue.dtsi | 73 ++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
index 85937de51e2..e3af97eac39 100644
--- a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
@@ -2,6 +2,7 @@
 
 #include <arm/armv7-m.dtsi>
 #include <mem.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 
 / {
 	clocks {
@@ -101,6 +102,78 @@
 			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
 		};
 
+		iom0: iom@40050000 {
+			reg = <0x40050000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <6 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
+		};
+
+		iom1: iom@40051000 {
+			reg = <0x40051000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <7 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
+		};
+
+		iom2: iom@40052000 {
+			reg = <0x40052000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <8 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
+		};
+
+		iom3: iom@40053000 {
+			reg = <0x40053000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <9 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
+		};
+
+		iom4: iom@40054000 {
+			reg = <0x40054000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <10 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
+		};
+
+		iom5: iom@40055000 {
+			reg = <0x40055000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
+		};
+
+		iom6: iom@40056000 {
+			reg = <0x40056000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <12 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
+		};
+
+		iom7: iom@40057000 {
+			reg = <0x40057000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <13 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
+		};
+
 		pinctrl: pin-controller@40010000 {
 			compatible = "ambiq,apollo4-pinctrl";
 			reg = <0x40010000 0x800>;