drivers: i2s_cavs: fix for I2S start after stop
Fixed an issue I2S wouldn't resume when started after a stop Added code to empty the TX/RX FIFOs upon stop TX stop is achieved by letting FIFO underrun, then changing state in ISR RX FIFO is read until empty when RX is stopped Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan
Anas Nashif
parent
d835714de3
commit
b72f5fd033
1 changed files with 89 additions and 76 deletions
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@ -185,6 +185,19 @@ static void i2s_tx_stream_disable(struct i2s_cavs_dev_data *,
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static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *,
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volatile struct i2s_cavs_ssp *const, struct device *);
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static inline void i2s_purge_stream_buffers(struct stream *strm,
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struct k_mem_slab *mem_slab)
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{
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void *buffer;
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while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(mem_slab, &buffer);
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}
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while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(mem_slab, &buffer);
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}
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}
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/* This function is executed in the interrupt context */
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static void i2s_dma_tx_callback(void *arg, u32_t channel,
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int status)
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@ -221,21 +234,23 @@ static void i2s_dma_tx_callback(void *arg, u32_t channel,
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ssp->ssc1 |= SSCR1_TSRE;
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k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
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}
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if (ret || status) {
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/*
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* DMA encountered an error (status != 0)
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* or
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* No bufers in input queue
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*/
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LOG_ERR("DMA status %08x channel %u k_msgq_get ret %d",
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status, channel, ret);
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strm->state = I2S_STATE_STOPPING;
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i2s_tx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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}
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break;
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case I2S_STATE_STOPPING:
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strm->state = I2S_STATE_READY;
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/* fall through */
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case I2S_STATE_ERROR:
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i2s_tx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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/* purge buffer queue */
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while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(dev_data->cfg.mem_slab, &buffer);
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}
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while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(dev_data->cfg.mem_slab, &buffer);
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}
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break;
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}
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}
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@ -271,8 +286,8 @@ static void i2s_dma_rx_callback(void *arg, u32_t channel, int status)
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if (ret != 0) {
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LOG_ERR("buffer alloc from slab %p err %d",
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dev_data->cfg.mem_slab, ret);
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strm->state = I2S_STATE_ERROR;
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i2s_rx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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strm->state = I2S_STATE_READY;
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} else {
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/* put buffer in input queue */
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ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
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@ -292,20 +307,8 @@ static void i2s_dma_rx_callback(void *arg, u32_t channel, int status)
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}
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break;
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case I2S_STATE_STOPPING:
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strm->state = I2S_STATE_READY;
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/* fall-through */
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case I2S_STATE_ERROR:
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i2s_rx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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/*
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* retrieve all buffers from input & output queues and free them
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*/
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while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(dev_data->cfg.mem_slab, &buffer);
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}
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while (k_msgq_get(&strm->out_queue, &buffer, K_NO_WAIT) == 0) {
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k_mem_slab_free(dev_data->cfg.mem_slab, &buffer);
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}
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strm->state = I2S_STATE_READY;
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break;
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}
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}
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@ -376,10 +379,10 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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/* reset SSP settings */
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/* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */
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ssc0 = SSCR0_MOD | SSCR0_PSP | SSCR0_RIM | SSCR0_TIM;
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ssc0 = SSCR0_MOD | SSCR0_PSP | SSCR0_RIM;
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/* sscr1 dynamic settings are SFRMDIR, SCLKDIR, SCFR */
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ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL | SSCR1_TSRE | SSCR1_RSRE;
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ssc1 = SSCR1_TTE | SSCR1_TTELP | SSCR1_TRAIL;
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/* sscr2 dynamic setting is LJDFD */
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ssc2 = 0U;
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@ -564,8 +567,12 @@ static int i2s_cavs_configure(struct device *dev, enum i2s_dir dir,
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/* enable port */
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ssp->ssc0 |= SSCR0_SSE;
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/* enable interrupt */
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irq_enable(dev_cfg->irq_id);
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dev_data->tx.state = I2S_STATE_READY;
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dev_data->rx.state = I2S_STATE_READY;
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return 0;
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}
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@ -608,6 +615,7 @@ static int i2s_tx_stream_start(struct i2s_cavs_dev_data *dev_data,
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/* Enable transmit operation */
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key = irq_lock();
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ssp->ssc1 |= SSCR1_TSRE;
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ssp->sstsa |= SSTSA_TXEN;
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irq_unlock(key);
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@ -655,6 +663,7 @@ static int i2s_rx_stream_start(struct i2s_cavs_dev_data *dev_data,
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/* Enable Receive operation */
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key = irq_lock();
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ssp->ssc1 |= SSCR1_RSRE;
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ssp->ssrsa |= SSRSA_RXEN;
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irq_unlock(key);
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@ -666,14 +675,22 @@ static void i2s_tx_stream_disable(struct i2s_cavs_dev_data *dev_data,
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struct device *dev_dma)
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{
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struct stream *strm = &dev_data->tx;
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unsigned int key;
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/* Disable DMA service request handshake logic. Handshake is
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* not required now since DMA is not in operation.
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/*
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* Enable transmit undderrun interrupt to allow notification
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* upon transmit FIFO being emptied.
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* Defer disabling of TX to the underrun processing in ISR
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*/
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ssp->sstsa &= ~SSTSA_TXEN;
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key = irq_lock();
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ssp->ssc0 &= ~SSCR0_TIM;
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irq_unlock(key);
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LOG_INF("Stopping TX stream & DMA channel %u", strm->dma_channel);
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LOG_INF("Stopping DMA channel %u for TX stream", strm->dma_channel);
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dma_stop(dev_dma, strm->dma_channel);
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/* purge buffers queued in the stream */
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i2s_purge_stream_buffers(strm, dev_data->cfg.mem_slab);
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}
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static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *dev_data,
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@ -681,6 +698,7 @@ static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *dev_data,
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struct device *dev_dma)
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{
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struct stream *strm = &dev_data->rx;
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u32_t data;
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/* Disable DMA service request handshake logic. Handshake is
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* not required now since DMA is not in operation.
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@ -689,6 +707,15 @@ static void i2s_rx_stream_disable(struct i2s_cavs_dev_data *dev_data,
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LOG_INF("Stopping RX stream & DMA channel %u", strm->dma_channel);
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dma_stop(dev_dma, strm->dma_channel);
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/* Empty the FIFO */
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while (ssp->sss & SSSR_RNE) {
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/* read the RX FIFO */
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data = ssp->ssd;
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}
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/* purge buffers queued in the stream */
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i2s_purge_stream_buffers(strm, dev_data->cfg.mem_slab);
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}
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static int i2s_cavs_trigger(struct device *dev, enum i2s_dir dir,
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@ -699,7 +726,7 @@ static int i2s_cavs_trigger(struct device *dev, enum i2s_dir dir,
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volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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struct stream *strm;
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unsigned int key;
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int ret;
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int ret = 0;
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strm = (dir == I2S_DIR_TX) ? &dev_data->tx : &dev_data->rx;
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@ -707,9 +734,9 @@ static int i2s_cavs_trigger(struct device *dev, enum i2s_dir dir,
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switch (cmd) {
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case I2S_TRIGGER_START:
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if (strm->state != I2S_STATE_READY) {
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irq_unlock(key);
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LOG_ERR("START trigger: invalid state %u", strm->state);
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return -EIO;
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ret = -EIO;
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break;
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}
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__ASSERT_NO_MSG(strm->mem_block == NULL);
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@ -723,63 +750,34 @@ static int i2s_cavs_trigger(struct device *dev, enum i2s_dir dir,
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}
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if (ret < 0) {
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irq_unlock(key);
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LOG_DBG("START trigger failed %d", ret);
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return ret;
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break;
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}
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strm->state = I2S_STATE_RUNNING;
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break;
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case I2S_TRIGGER_STOP:
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if (strm->state != I2S_STATE_RUNNING) {
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irq_unlock(key);
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LOG_DBG("STOP trigger: invalid state");
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return -EIO;
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}
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strm->state = I2S_STATE_STOPPING;
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break;
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case I2S_TRIGGER_DRAIN:
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case I2S_TRIGGER_DROP:
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if (strm->state != I2S_STATE_RUNNING) {
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irq_unlock(key);
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LOG_DBG("DRAIN trigger: invalid state");
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return -EIO;
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LOG_DBG("STOP/DRAIN/DROP trigger: invalid state");
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ret = -EIO;
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break;
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}
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strm->state = I2S_STATE_STOPPING;
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break;
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case I2S_TRIGGER_DROP:
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if (strm->state == I2S_STATE_NOT_READY) {
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irq_unlock(key);
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LOG_DBG("DROP trigger: invalid state");
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return -EIO;
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}
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if (dir == I2S_DIR_TX) {
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i2s_tx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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} else {
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i2s_rx_stream_disable(dev_data, ssp, dev_data->dev_dma);
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}
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strm->state = I2S_STATE_READY;
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break;
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case I2S_TRIGGER_PREPARE:
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if (strm->state != I2S_STATE_ERROR) {
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irq_unlock(key);
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LOG_DBG("PREPARE trigger: invalid state");
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return -EIO;
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}
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strm->state = I2S_STATE_READY;
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break;
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default:
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irq_unlock(key);
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LOG_ERR("Unsupported trigger command");
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return -EINVAL;
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ret = -EINVAL;
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}
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irq_unlock(key);
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return 0;
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return ret;
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}
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static int i2s_cavs_read(struct device *dev, void **mem_block, size_t *size)
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@ -789,8 +787,7 @@ static int i2s_cavs_read(struct device *dev, void **mem_block, size_t *size)
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void *buffer;
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int ret = 0;
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if ((strm->state == I2S_STATE_NOT_READY) ||
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(strm->state == I2S_STATE_ERROR)) {
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if (strm->state == I2S_STATE_NOT_READY) {
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LOG_ERR("invalid state %d", strm->state);
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return -EIO;
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}
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@ -834,15 +831,28 @@ static void i2s_cavs_isr(void *arg)
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struct device *dev = (struct device *)arg;
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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volatile struct i2s_cavs_ssp *const ssp = dev_cfg->regs;
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u32_t temp;
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struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
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u32_t status;
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/* clear IRQ */
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temp = ssp->sss;
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ssp->sss = temp;
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/* clear interrupts */
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status = ssp->sss;
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ssp->sss = status;
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if (status & SSSR_TUR) {
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/*
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* transmit underrun occurred.
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* 1. disable transmission
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* 2. disable underrun interrupt
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*/
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ssp->sstsa &= ~SSTSA_TXEN;
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ssp->ssc0 |= SSCR0_TIM;
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dev_data->tx.state = I2S_STATE_READY;
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}
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}
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static int i2s_cavs_initialize(struct device *dev)
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{
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const struct i2s_cavs_config *const dev_cfg = DEV_CFG(dev);
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struct i2s_cavs_dev_data *const dev_data = DEV_DATA(dev);
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dev_data->dev_dma = device_get_binding(CONFIG_I2S_CAVS_DMA_NAME);
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@ -861,6 +871,9 @@ static int i2s_cavs_initialize(struct device *dev)
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k_msgq_init(&dev_data->rx.out_queue, (char *)dev_data->rx.out_msgs,
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sizeof(void *), I2S_CAVS_BUF_Q_LEN);
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/* register ISR */
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dev_cfg->irq_connect();
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dev_data->tx.state = I2S_STATE_NOT_READY;
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dev_data->rx.state = I2S_STATE_NOT_READY;
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