diff --git a/boards/arm/stm32l496g_disco/Kconfig.board b/boards/arm/stm32l496g_disco/Kconfig.board
new file mode 100644
index 00000000000..0538d444ab3
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/Kconfig.board
@@ -0,0 +1,11 @@
+# Kconfig - STM32L496G Discovery board configuration
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_STM32L496G_DISCO
+	bool "STM32L496G Discovery Development Board"
+	depends on SOC_STM32L496XG
diff --git a/boards/arm/stm32l496g_disco/Kconfig.defconfig b/boards/arm/stm32l496g_disco/Kconfig.defconfig
new file mode 100644
index 00000000000..cb3c08e07d4
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/Kconfig.defconfig
@@ -0,0 +1,14 @@
+# Kconfig - STM32L476G Nucleo board configuration
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_STM32L496G_DISCO
+
+config BOARD
+	default stm32l496g_disco
+
+endif # BOARD_STM32L496G_DISCO
diff --git a/boards/arm/stm32l496g_disco/Makefile b/boards/arm/stm32l496g_disco/Makefile
new file mode 100644
index 00000000000..c925263c43a
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/Makefile
@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o
diff --git a/boards/arm/stm32l496g_disco/board.h b/boards/arm/stm32l496g_disco/board.h
new file mode 100644
index 00000000000..21cb7fa721e
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/board.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2015 Intel Corporation
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* LD2 green LED */
+#define LD2_GPIO_PORT	"GPIOB"
+#define LD2_GPIO_PIN	13
+
+/* Create aliases to make the basic samples work */
+#define LED0_GPIO_PORT	LD2_GPIO_PORT
+#define LED0_GPIO_PIN	LD2_GPIO_PIN
+
+#endif /* __INC_BOARD_H */
diff --git a/boards/arm/stm32l496g_disco/doc/img/en.stm32l496g-disco.jpg b/boards/arm/stm32l496g_disco/doc/img/en.stm32l496g-disco.jpg
new file mode 100644
index 00000000000..798f5f3fa4c
Binary files /dev/null and b/boards/arm/stm32l496g_disco/doc/img/en.stm32l496g-disco.jpg differ
diff --git a/boards/arm/stm32l496g_disco/doc/stm32l496g_disco.rst b/boards/arm/stm32l496g_disco/doc/stm32l496g_disco.rst
new file mode 100644
index 00000000000..187442ab02b
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/doc/stm32l496g_disco.rst
@@ -0,0 +1,255 @@
+.. _stm32l496g_disco_board:
+
+ST STM32L496G Discovery
+########################
+
+Overview
+********
+
+The STM32L496G Discovery board features an ARM Cortex-M4 based STM32L496AG MCU
+with a wide range of connectivity support and configurations. Here are
+some highlights of the STM32L496G Discovery board:
+
+
+- STM32L496AGI6 microcontroller featuring 1 Mbyte of Flash memory and 320 Kbytes of RAM in an UFBGA169 package
+- 1.54 inch 240 x 240 pixel-TFT color LCD with parallel interface
+- SAI Audio CODEC, with a stereo headset jack, including analog microphone input
+- Stereo digital MEMS microphones
+- microSD card connector (card included)
+- Camera 8 bit-connector
+- 8 Mbit-PSRAM
+- IDD measurement
+- 64 Mbit-Quad-SPI Flash
+- USB OTG FS with Micro-AB connector
+- Two types of extension resources:
+
+       - STMod+ and PMOD connectors
+       - Compatible Arduino™ Uno V3 connectors
+
+- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
+- 5 source options for power supply
+
+       - ST-LINK/V2-1 USB connector
+       - User USB FS connector
+       - VIN from Arduino™ connector
+       - 5 V from Arduino™ connector
+       - USB charger
+       - USB VBUS or external source(3.3V, 5V, 7 - 12V)
+       - Power management access point
+
+- 8 LEDs
+- Reset push button
+- 4 direction-joystick with selection
+
+.. image:: img/en.stm32l496g-disco.jpg
+     :width: 450px
+     :align: center
+     :height: 394px
+     :alt: STM32L496G Discovery
+
+More information about the board can be found at the `STM32L496G Discovery website`_.
+
+Hardware
+********
+
+The STM32L496AG SoC provides the following hardware capabilities:
+
+- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 μA/MHz run mode)
+- Core: ARM® 32-bit Cortex®-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
+- Clock Sources:
+
+        - 4 to 48 MHz crystal oscillator
+        - 32 kHz crystal oscillator for RTC (LSE)
+        - Internal 16 MHz factory-trimmed RC (±1%)
+        - Internal low-power 32 kHz RC (±5%)
+        - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)
+        - Internal 48 MHz with clock recovery
+        - 3 PLLs for system clock, USB, audio, ADC
+
+- RTC with HW calendar, alarms and calibration
+- LCD 8 × 40 or 4 × 44 with step-up converter
+- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
+- 16x timers:
+
+        - 2x 16-bit advanced motor-control
+        - 2x 32-bit and 5x 16-bit general purpose
+        - 2x 16-bit basic
+        - 2x low-power 16-bit timers (available in Stop mode)
+        - 2x watchdogs
+        - SysTick timer
+
+- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
+- Memories
+
+        - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
+        - 320 KB of SRAM including 64 KB with hardware parity check
+        - External memory interface for static memories supporting SRAM, PSRAM, NOR, and NAND memories
+        - Quad SPI memory interface
+
+- 4x digital filters for sigma delta modulator
+- Rich analog peripherals (independent supply)
+
+        - 3× 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 μA/MSPS
+        - 2x 12-bit DAC, low-power sample and hold
+        - 2x operational amplifiers with built-in PGA
+        - 2x ultra-low-power comparators
+
+- 20x communication interfaces
+
+        - USB OTG 2.0 full-speed, LPM and BCD
+        - 2x SAIs (serial audio interface)
+        - 4x I2C FM+(1 Mbit/s), SMBus/PMBus
+        - 5x USARTs (ISO 7816, LIN, IrDA, modem)
+        - 1x LPUART
+        - 3x SPIs (4x SPIs with the Quad SPI)
+        - 2x CAN (2.0B Active) and SDMMC interface
+        - SWPMI single wire protocol master I/F
+        - IRTIM (Infrared interface)
+
+- 14-channel DMA controller
+- True random number generator
+- CRC calculation unit, 96-bit unique ID
+- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™
+
+
+More information about STM32L496AG can be found here:
+       - `STM32L496AG on www.st.com`_
+       - `STM32L496 reference manual`_
+
+Supported Features
+==================
+
+The Zephyr stm32l496g_disco board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+
+	``boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig``
+
+
+Connections and IOs
+===================
+
+STM32L496G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+For mode details please refer to `STM32L496G Discovery board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART_1_TX : PB6
+- UART_1_RX : PG10
+- UART_2_TX : PA2
+- UART_2_RX : PD6
+- I2C_1_SCL : PB8
+- I2C_1_SDA : PB7
+- PWM_2_CH1 : PA0
+- LD2 : PB13
+
+System Clock
+------------
+
+STM32L496G Discovery System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
+driven by 16MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+STM32L496G Discovery board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2.
+Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface.
+This interface is not supported by the openocd version 0.9 included by the Zephyr SDK v0.9,
+use openocd v0.10.0 from the openocd-stm32 project on GitHub to get the minimum set of scripts
+needed to flash and debug STM32 development boards.
+
+.. code-block:: console
+
+   $ git clone  https://github.com/erwango/openocd-stm32.git
+
+Then follow instructions in README.md
+
+
+Flashing an application to STM32L496G Discovery
+-----------------------------------------------
+
+The sample application :ref:`hello_world` is being used in this tutorial:
+
+To build the Zephyr kernel and application, enter:
+
+.. code-block:: console
+
+   $ cd <zephyr_root_path>
+   $ source zephyr-env.sh
+   $ cd $ZEPHYR_BASE/samples/hello_world/
+   $ make BOARD=stm32l496g_disco
+
+Connect the STM32L496G Discovery to your host computer using the USB port.
+Then, enter the following command:
+
+.. code-block:: console
+
+   $ cd <openocd-stm32_path>
+   $ stm32_flsh l4 $ZEPHYR_BASE/samples/hello_world/outdir/stm32l496g_disco/zephyr.bin
+
+Run a serial host program to connect with your Discovery board.
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+You should see the following message:
+
+.. code-block:: console
+
+   $ Hello World! arm
+
+
+Debugging
+=========
+
+Access gdb with the following make command:
+
+.. code-block:: console
+
+   $ cd <openocd-stm32_path>
+   $ stm32_dbg l4 $ZEPHYR_BASE/samples/hello_world/outdir/stm32l496g_disco/zephyr.elf
+
+.. _STM32L496G Discovery website:
+   http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
+
+.. _STM32L496G Discovery board User Manual:
+   http://www.st.com/resource/en/user_manual/dm00353127.pdf
+
+.. _STM32L496AG on www.st.com:
+   http://www.st.com/en/microcontrollers/stm32l496ag.html
+
+.. _STM32L496 reference manual:
+   http://www.st.com/resource/en/reference_manual/DM00083560.pdf
diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig b/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig
new file mode 100644
index 00000000000..b9610c602a7
--- /dev/null
+++ b/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_BOARD_STM32L496G_DISCO=y
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32L4X=y
+CONFIG_SOC_STM32L496XG=y
+CONFIG_CORTEX_M_SYSTICK=y
+# 80MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_STM32=y
+CONFIG_UART_STM32_PORT_2=y
+
+# enable pinmux
+CONFIG_PINMUX=y
+CONFIG_PINMUX_STM32=y
+
+# enable GPIOs
+CONFIG_GPIO=y
+CONFIG_GPIO_STM32=y
+CONFIG_GPIO_STM32_PORTA=y
+CONFIG_GPIO_STM32_PORTB=y
+CONFIG_GPIO_STM32_PORTC=y
+CONFIG_GPIO_STM32_PORTD=y
+CONFIG_GPIO_STM32_PORTE=y
+CONFIG_GPIO_STM32_PORTF=y
+CONFIG_GPIO_STM32_PORTG=y
+CONFIG_GPIO_STM32_PORTH=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_STM32_CUBE=y
+# SYSCLK selection
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# PLL configuration
+CONFIG_CLOCK_STM32_PLL_SRC_HSI
+# produce 80MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=20
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
+CONFIG_CLOCK_STM32_PLL_R_DIVISOR=4
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=1
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1
+
+# console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
+
+#enable pwm
+CONFIG_PWM=y
+CONFIG_PWM_STM32=y
+CONFIG_PWM_STM32_2=y
+
+#enable DTS
+CONFIG_HAS_DTS=y
diff --git a/drivers/pinmux/Makefile b/drivers/pinmux/Makefile
index 4a0cee01ff7..0e5adf9eff5 100644
--- a/drivers/pinmux/Makefile
+++ b/drivers/pinmux/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_BOARD_96B_CARBON) += stm32/pinmux_board_carbon.o
 obj-$(CONFIG_BOARD_NUCLEO_L476RG) += stm32/pinmux_board_nucleo_l476rg.o
 obj-$(CONFIG_BOARD_NUCLEO_L432KC) += stm32/pinmux_board_nucleo_l432kc.o
 obj-$(CONFIG_BOARD_DISCO_L475_IOT1) += stm32/pinmux_board_disco_l475_iot1.o
+obj-$(CONFIG_BOARD_STM32L496G_DISCO) += stm32/pinmux_board_stm32l496g_disco.o
 obj-$(CONFIG_BOARD_OLIMEXINO_STM32) += stm32/pinmux_board_olimexino_stm32.o
 obj-$(CONFIG_BOARD_STM32_MINI_A15) += stm32/pinmux_board_stm32_mini_a15.o
 obj-$(CONFIG_PINMUX_QMSI) += pinmux_qmsi.o
diff --git a/drivers/pinmux/stm32/pinmux_board_stm32l496g_disco.c b/drivers/pinmux/stm32/pinmux_board_stm32l496g_disco.c
new file mode 100644
index 00000000000..8e0ff4dd05d
--- /dev/null
+++ b/drivers/pinmux/stm32/pinmux_board_stm32l496g_disco.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+#include "pinmux/pinmux.h"
+
+#include "pinmux_stm32.h"
+
+/* pin assignments for STM32L476G-DISCO board */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_STM32_PORT_1
+	{STM32_PIN_PB6,  STM32L4X_PINMUX_FUNC_PB6_USART1_TX},
+	{STM32_PIN_PG10, STM32L4X_PINMUX_FUNC_PG10_USART1_RX},
+#endif	/* CONFIG_UART_STM32_PORT_1 */
+#ifdef CONFIG_UART_STM32_PORT_2
+	{STM32_PIN_PA2, STM32L4X_PINMUX_FUNC_PA2_USART2_TX},
+	{STM32_PIN_PD6, STM32L4X_PINMUX_FUNC_PD6_USART2_RX},
+#endif	/* CONFIG_UART_STM32_PORT_2 */
+#ifdef CONFIG_I2C_1
+	{STM32_PIN_PB8, STM32L4X_PINMUX_FUNC_PB8_I2C1_SCL},
+	{STM32_PIN_PB7, STM32L4X_PINMUX_FUNC_PB7_I2C1_SDA},
+#endif /* CONFIG_I2C_1 */
+#ifdef CONFIG_PWM_STM32_2
+	{STM32_PIN_PA0, STM32L4X_PINMUX_FUNC_PA0_PWM2_CH1},
+#endif /* CONFIG_PWM_STM32_2 */
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
+	 CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
diff --git a/dts/arm/Makefile b/dts/arm/Makefile
index 54a882a3be5..488a9bc09e2 100644
--- a/dts/arm/Makefile
+++ b/dts/arm/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_BOARD_NUCLEO_F413ZH)	=	nucleo_f413zh.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F103RB)	=	nucleo_f103rb.dts_compiled
 dtb-$(CONFIG_BOARD_STM3210C_EVAL)	=	stm3210c_eval.dts_compiled
 dtb-$(CONFIG_BOARD_STM32_MINI_A15)	=	stm32_mini_a15.dts_compiled
+dtb-$(CONFIG_BOARD_STM32L496G_DISCO)	=	stm32l496g_disco.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F334R8)	=	nucleo_f334r8.dts_compiled
 dtb-$(CONFIG_BOARD_STM32373C_EVAL)	=	stm32373c_eval.dts_compiled
 dtb-$(CONFIG_BOARD_96B_NITROGEN)	=	96b_nitrogen.dts_compiled
diff --git a/dts/arm/stm32l496g_disco.dts b/dts/arm/stm32l496g_disco.dts
new file mode 100644
index 00000000000..65bab5a6b04
--- /dev/null
+++ b/dts/arm/stm32l496g_disco.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/stm32l496.dtsi>
+
+/ {
+	model = "STMicroelectronics STM32L496G-DISCO board";
+	compatible = "st,stm32l496g-disco", "st,stm32l496";
+
+	chosen {
+		zephyr,console = &usart2;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart2 {
+	current-speed = <115200>;
+	status = "ok";
+};
diff --git a/dts/arm/stm32l496g_disco.fixup b/dts/arm/stm32l496g_disco.fixup
new file mode 100644
index 00000000000..ac9af9a7608
--- /dev/null
+++ b/dts/arm/stm32l496g_disco.fixup
@@ -0,0 +1,32 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS	ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_1_BAUD_RATE	ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_1_IRQ_PRI	ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define PORT_1_IRQ				ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define PORT_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define PORT_3_IRQ				ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS	ST_STM32_USART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_4_BAUD_RATE	ST_STM32_USART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_4_IRQ_PRI	ST_STM32_USART_40004C00_IRQ_0_PRIORITY
+#define PORT_4_IRQ				ST_STM32_USART_40004C00_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_5_BASE_ADDRESS	ST_STM32_USART_40005000_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_5_BAUD_RATE	ST_STM32_USART_40005000_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_5_IRQ_PRI	ST_STM32_USART_40005000_IRQ_0_PRIORITY
+#define PORT_5_IRQ				ST_STM32_USART_40005000_IRQ_0
diff --git a/scripts/sanity_chk/arches/arm.ini b/scripts/sanity_chk/arches/arm.ini
index 2b675ddff54..866e33f67a1 100644
--- a/scripts/sanity_chk/arches/arm.ini
+++ b/scripts/sanity_chk/arches/arm.ini
@@ -8,7 +8,7 @@ platforms = qemu_cortex_m3 frdm_k64f arduino_due nucleo_f103rb stm32_mini_a15
             stm3210c_eval nucleo_f334r8 stm32373c_eval mps2_an385 frdm_kw41z
             sam_e70_xplained curie_ble nrf52_blenano2 hexiwear_kw40z
             cc3220sf_launchxl frdm_kl25z disco_l475_iot1 nucleo_l432kc
-            nucleo_f413zh
+            nucleo_f413zh stm32l496g_disco
 
 supported_toolchains = zephyr gccarmemb