soc: npcx: add soc drivers for npcx9 series.

This CL adds the soc drivers for npcx9 series. There are two soc part
numbers, npcx9m3f and npcx9m6f, are introduced. We also move soc family
configurations from /nuvoton_npcx/npcx7/Kconfig.soc to
nuvoton_npcx/Kconfig.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>

soc/arm/nuvoton_npcx/Kconfig

@@ -163,4 +163,20 @@ endif # NPCX_HEADER
 # Select SoC Part No. and configuration options
 source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
 
+config SOC_POWER_MANAGEMENT
+	bool "System Power Management in NPCX family"
+	depends on SOC_FAMILY_NPCX
+	help
+	  This option enables the board to implement SoC-specific power
+	  management policies whenever the kernel becomes idle. The power
+	  management subsystem will restore to the active state until an
+	  wake-up event is received no matter the system timer is expired or
+	  the other signals occurred such as GPIO, host access, and so on.
+
+config SOC_POWER_MANAGEMENT_TRACE
+	bool "Trace System Power Management in NPCX family"
+	depends on SOC_POWER_MANAGEMENT
+	help
+	  Internal config to enable runtime power management traces.
+
 endif # SOC_FAMILY_NPCX

soc/arm/nuvoton_npcx/npcx7/Kconfig.soc

@@ -17,19 +17,3 @@ config SOC_NPCX7M7FC
 	bool "NPCX7M7FC"
 
 endchoice
-
-config SOC_POWER_MANAGEMENT
-	bool "System Power Management in NPCX series"
-	depends on SOC_SERIES_NPCX7
-	help
-	  This option enables the board to implement SoC specific power
-	  management policies whenever the kernel becomes idle. The power
-	  management subsystem will restore to the active state until an
-	  wake-up event is received no matter the system timer is expired or
-	  the other signals occurred such as GPIO, host access, and so on.
-
-config SOC_POWER_MANAGEMENT_TRACE
-	bool "Trace System Power Management in NPCX series"
-	depends on SOC_POWER_MANAGEMENT
-	help
-	  Internal config to enable runtime power management traces.

soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_sources(
+  soc.c
+)

soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f

@@ -0,0 +1,11 @@
+# Nuvoton Cortex-M4 Embedded Controller
+
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NPCX9M3F
+
+config SOC
+	default "npcx9m3f"
+
+endif # SOC_NPCX9M3F

soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f

@@ -0,0 +1,11 @@
+# Nuvoton Cortex-M4 Embedded Controller
+
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NPCX9M6F
+
+config SOC
+	default "npcx9m6f"
+
+endif # SOC_NPCX9M6F

soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series

@@ -0,0 +1,121 @@
+# Nuvoton Cortex-M4 Embedded Controller
+
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NPCX9
+
+config SOC_SERIES
+	default "npcx9"
+
+config NUM_IRQS
+	default 64
+
+config CORTEX_M_SYSTICK
+	default !NPCX_ITIM_TIMER
+	help
+	  Disable Cortex-M system tick if NPCX_ITIM_TIMER is enabled.
+
+config CLOCK_CONTROL_NPCX
+	default y
+	depends on CLOCK_CONTROL
+	help
+	  Enable support for NPCX clock controller driver. The NPCX clock
+	  controller generates both Low-Frequency clock domain (32.768 KHz,
+	  i.e. LFCLK clock signal) and High-Frequency clock signals (OSC_CLK,
+	  AHB6_CLK, APBn_CLK, and FMCLK) for the Core domain modules.
+
+config UART_NPCX
+	default y
+	depends on SERIAL
+	help
+	  Enable support for NPCX UART driver. In NPCX9 series, it includes 4
+	  modules which support full-duplex asynchronous receiver-transmitter
+	  with 16-byte transmit and receive buffers.
+
+config GPIO_NPCX
+	default y
+	depends on GPIO
+	help
+	  Enable support for NPCX GPIO driver. In NPCX9 series, it includes 16
+	  ports that support input/output, input-only and output-only
+	  configurations.
+
+config PWM_NPCX
+	default y
+	depends on PWM
+	help
+	  Enable support for NPCX PWM driver. In NPCX9 series, it includes 8
+	  modules. Each module generates a single 16-bit PWM output. A 16-bit
+	  clock prescaler and a 16-bit counter determine the cycle time, the
+	  minimum possible pulse width and the duty cycle steps.
+
+config ADC_NPCX
+	default y
+	depends on ADC
+	help
+	  Enable support for NPCX ADC driver. In NPCX9 series, it includes a
+	  10-bit resolution Analog-to-Digital Converter (ADC). Up to 12 voltage
+	  inputs can be measured and a internal voltage reference (VREF), 2.816V
+	  (typical) is used for measurement.
+
+config WDT_NPCX
+	default y
+	depends on WATCHDOG
+	help
+	  Enable support for NPCX Watchdog driver. Besides watchdog
+	  functionality, it also provides the protection mechanism over software
+	  execution. After setting the configuration registers, the software can
+	  lock it to provide a higher level of protection against subsequent
+	  erroneous software action. Once a section of the TWD is locked, only
+	  reset or the unlock sequence releases it.
+
+config ESPI_NPCX
+	default y
+	depends on ESPI
+	help
+	  Enable support for NPCX ESPI driver. The Intel Enhanced Serial
+	  Peripheral Interface (eSPI) provides a path for migrating host
+	  sub-devices via LPC to a lower pin count, higher bandwidth bus.
+	  So far, this driver supports all of functionalities beside flash
+	  channel support. It will be supported in the future. Please refer
+	  https://www.intel.com/content/www/us/en/support/articles/000020952/
+	  software/chipset-software.html for more detail.
+
+config I2C_NPCX
+	default y
+	depends on I2C
+	help
+	  Enable support for NPCX I2C driver. The NPCX SMB/I2C modules provides
+	  full support for a two-wire SMBus/I2C synchronous serial interface.
+	  Each interface is a two-wire serial interface that is compatible with
+	  both Intel SMBus and Philips I2C physical layer. There are 8 SMBus
+	  modules and 10 buses in NPCX9 series.
+
+config TACH_NPCX
+	default y
+	depends on SENSOR
+	help
+	  Enable support for NPCX tachometer sensor driver. The NPCX9 series
+	  contains two tachometer (TACH) modules that contains two counters
+	  (counter A and B). They are used to capture/compare a counter value
+	  when an event is generated on comparison of signals match.
+
+if SOC_POWER_MANAGEMENT
+
+config PM
+	default y if SYS_CLOCK_EXISTS
+	help
+	  Enable the kernel handles extra power management policies whenever
+	  system enters idle state.
+
+config PM_DEVICE
+	default y
+	help
+	  Enable device power management support.
+
+endif # SOC_POWER_MANAGEMENT
+
+source "soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9*"
+
+endif # SOC_SERIES_NPCX9

soc/arm/nuvoton_npcx/npcx9/Kconfig.series

@@ -0,0 +1,15 @@
+# Nuvoton Cortex-M4 Embedded Controller NPCX9 series
+
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NPCX9
+	bool "Nuvoton NPCX9 Series"
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select SOC_FAMILY_NPCX
+	help
+	  Enable support for Nuvoton NPCX9 series

soc/arm/nuvoton_npcx/npcx9/Kconfig.soc

@@ -0,0 +1,16 @@
+# Nuvoton NPCX9 EC series
+
+# Copyright (c) 2021 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "NPCX9 Selection"
+	depends on SOC_SERIES_NPCX9
+
+config SOC_NPCX9M3F
+	bool "NPCX9M3F"
+
+config SOC_NPCX9M6F
+	bool "NPCX9M6F"
+
+endchoice

soc/arm/nuvoton_npcx/npcx9/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/nuvoton_npcx/npcx9/soc.c

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+
+static int soc_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/arm/nuvoton_npcx/npcx9/soc.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_SOC_H_
+#define _NUVOTON_NPCX_SOC_H_
+
+/* CMSIS required definitions */
+#define __FPU_PRESENT  CONFIG_CPU_HAS_FPU
+#define __MPU_PRESENT  CONFIG_CPU_HAS_ARM_MPU
+
+/* Add include for DTS generated information */
+#include <devicetree.h>
+
+#include <reg/reg_access.h>
+#include <reg/reg_def.h>
+#include <soc_dt.h>
+#include <soc_clock.h>
+#include <soc_pins.h>
+#include <soc_power.h>
+
+#endif /* _NUVOTON_NPCX_SOC_H_ */