soc: arm: add infineon_xmc series support

Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash

init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.

Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>

CODEOWNERS

@@ -34,6 +34,7 @@
 /soc/arm/atmel_sam/same70/                @nandojve
 /soc/arm/atmel_sam/samv71/                @nandojve
 /soc/arm/bcm*/                            @sbranden
+/soc/arm/infineon_xmc/                    @parthitce
 /soc/arm/nxp*/                            @MaureenHelm
 /soc/arm/nordic_nrf/                      @ioannisg
 /soc/arm/qemu_cortex_a53/                 @carlocaione
@@ -247,6 +248,7 @@
 /dts/arm/atmel/samv71*                    @nandojve
 /dts/arm/atmel/                           @galak
 /dts/arm/broadcom/                        @sbranden
+/dts/arm/infineon/                        @parthitce
 /dts/arm/qemu-virt/                       @carlocaione
 /dts/arm/st/                              @erwango
 /dts/arm/ti/cc13?2*                       @bwitherspoon

dts/arm/infineon/xmc4500.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <infineon/xmc4xxx.dtsi>
+
+&psram1 {
+	reg = <0x10000000 DT_SIZE_K(64)>;
+};
+
+&dsram1 {
+	reg = <0x20000000 DT_SIZE_K(64)>;
+};
+
+&dsram2 {
+	reg = <0x30000000 DT_SIZE_K(32)>;
+};
+
+&flash0 {
+	reg = <0xc000000 DT_SIZE_M(1)>;
+};

dts/arm/infineon/xmc4xxx.dtsi

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* TODO: Add psram1 & dsram2 to MEMORY layout of linker */
+	psram1: memory@10000000 {
+		compatible = "mmio-sram";
+	};
+
+	dsram1: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	dsram2: memory@30000000 {
+		compatible = "mmio-sram";
+	};
+
+	flash0: serial-flash@c000000 {
+		compatible = "serial-flash";
+	};
+
+	sysclk: system-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <120000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		usic0ch0: usic@40030000 {
+			reg = <0x40030000 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		usic0ch1: usic@40030200 {
+			reg = <0x40030200 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		usic1ch0: usic@48020000 {
+			reg = <0x48020000 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		usic1ch1: usic@48020200 {
+			reg = <0x48020200 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		usic2ch0: usic@48024000 {
+			reg = <0x48024000 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		usic2ch1: usic@48024200 {
+			reg = <0x48024200 0x1ff>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <6>;
+};

modules/Kconfig

@@ -10,6 +10,7 @@ source "modules/Kconfig.civetweb"
 source "modules/Kconfig.cmsis"
 source "modules/Kconfig.cypress"
 source "modules/Kconfig.imx"
+source "modules/Kconfig.infineon"
 source "modules/Kconfig.libmetal"
 source "modules/Kconfig.loramac-node"
 source "modules/Kconfig.mbedtls"

modules/Kconfig.infineon

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+config HAS_XMCLIB
+	bool
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_XMC
+
+if HAS_XMCLIB
+
+config HAS_XMCLIB_UART
+	bool
+	help
+	  Enable XMCLIB Universal asynchronous receiver transmitter (UART)
+
+endif # HAS_XMCLIB

soc/arm/infineon_xmc/4xxx/CMakeLists.txt

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+zephyr_sources(soc.c)
+zephyr_linker_sources(NOINIT noinit.ld)

soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# XMC 4xxx series configuration options
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+if SOC_SERIES_XMC_4XXX
+
+config SOC_SERIES
+	default "4xxx"
+
+config NUM_IRQS
+	default 112
+
+config UART_XMC4XXX
+	default y
+	depends on SERIAL
+
+source "soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc*"
+
+endif # SOC_SERIES_XMC_4XXX

soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500

@@ -0,0 +1,18 @@
+# Infineon XMC4500 relax kit platform configuration options
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_XMC4500
+
+config SOC
+	default "XMC4500"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 120000000
+
+config NUM_IRQS
+	default 110
+
+endif # SOC_XMC4500

soc/arm/infineon_xmc/4xxx/Kconfig.series

@@ -0,0 +1,16 @@
+# XMC4xxx MCU series
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_XMC_4XXX
+	bool "XMC 4xxx Series MCU"
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select SOC_FAMILY_XMC
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	help
+	  Enable support for XMC 4xxx MCU series

soc/arm/infineon_xmc/4xxx/Kconfig.soc

@@ -0,0 +1,30 @@
+# XMC 4xxx MCU line
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "XMC 4xxx MCU Selection"
+	depends on SOC_SERIES_XMC_4XXX
+
+config SOC_XMC4500
+	bool "SOC_XMC4500"
+	select HAS_XMCLIB
+
+endchoice
+
+if SOC_SERIES_XMC_4XXX
+
+config SOC_PART_NUMBER_F100X1024
+	bool
+
+config SOC_PART_NUMBER_XMC_4XXX
+	string
+	default "F100x1024" if SOC_PART_NUMBER_F100X1024
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.
+
+endif # SOC_SERIES_XMC_4XXX

soc/arm/infineon_xmc/4xxx/linker.ld

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images and XIP images.
+ */
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/infineon_xmc/4xxx/noinit.ld

@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ *
+ * Extracted from: infineon/XMCLib/devices/XMC4500/Source/GCC/XMC4500x1024.ld
+ */
+
+/* .no_init section contains chipid, SystemCoreClock and trimming data */
+KEEP(*(.no_init))

soc/arm/infineon_xmc/4xxx/soc.c

@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ *
+ */
+
+#include <kernel.h>
+#include <init.h>
+#include <soc.h>
+
+#define PMU_FLASH_WS		(0x3U)
+
+void z_platform_init(void)
+{
+	u32_t temp;
+
+	/* setup flash wait state */
+	temp = FLASH0->FCON;
+	temp &= ~FLASH_FCON_WSPFLASH_Msk;
+	temp |= PMU_FLASH_WS;
+	FLASH0->FCON = temp;
+
+	/* configure PLL & system clock */
+	SystemCoreClockSetup();
+}

soc/arm/infineon_xmc/4xxx/soc.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2020 Linumiz
+ * Author: Parthiban Nallathambi <parthiban@linumiz.com>
+ *
+ */
+
+/* Add include for DTS generated information */
+#include <devicetree.h>
+#include <system_XMC4500.h>
+#include <XMC4500.h>

soc/arm/infineon_xmc/CMakeLists.txt

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+add_subdirectory(${SOC_SERIES})

soc/arm/infineon_xmc/Kconfig

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+config SOC_FAMILY_XMC
+	bool
+	select HAS_SEGGER_RTT
+	select PLATFORM_SPECIFIC_INIT
+
+if SOC_FAMILY_XMC
+
+config SOC_FAMILY
+	string
+	default "infineon_xmc"
+
+source "soc/arm/infineon_xmc/*/Kconfig.soc"
+
+config SOC_PART_NUMBER
+	default SOC_PART_NUMBER_XMC_4XXX if SOC_SERIES_XMC_4XXX
+
+endif # SOC_FAMILY_XMC

soc/arm/infineon_xmc/Kconfig.defconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+source "soc/arm/infineon_xmc/*/Kconfig.defconfig.series"

soc/arm/infineon_xmc/Kconfig.soc

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Linumiz
+# Author: Parthiban Nallathambi <parthiban@linumiz.com>
+
+source "soc/arm/infineon_xmc/*/Kconfig.series"

west.yml

@@ -52,6 +52,9 @@ manifest:
     - name: hal_cypress
       revision: a12d92816a53a521d79cefcf5c38b9dc8a4fed6e
       path: modules/hal/cypress
+    - name: hal_infineon
+      revision: f1fa8241f8786198ba41155413243de36ed878a5
+      path: modules/hal/infineon
     - name: hal_nordic
       revision: e1168a2f3290f5ca17ec0c47efbf6c601c60108a
       path: modules/hal/nordic