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dts: power: ambiq: change to use ambiq HAL to do power-on config

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Changed to use ambiq HAL to do power-on config, no need to bind
pwrcfg any more

Signed-off-by: Hao Luo <hluo@ambiq.com>
This commit is contained in:
Hao Luo 2025-04-18 14:39:26 +08:00 • committed by Benjamin Cabé
commit b64a56362d
9 changed files with 5 additions and 117 deletions
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38
drivers/serial/uart_pl011_ambiq.h
View file

@ -168,48 +168,18 @@ static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action
}
#endif /* CONFIG_PM_DEVICE */
/* Problem: writes to power configure register takes some time to take effective.
* Solution: Check device's power status to ensure that register has taken effective.
* Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
*/
#if defined(CONFIG_SOC_SERIES_APOLLO3X)
#define DEVPWRSTATUS_OFFSET 0x10
#define HCPA_MASK 0x4
#define AMBIQ_UART_DEFINE(n) \
PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
static int pwr_on_ambiq_uart_##n(void) \
{ \
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
while (!(sys_read32(pwr_status_addr) & HCPA_MASK)) { \
}; \
return 0; \
uint32_t module = (DT_INST_REG_ADDR(n) - UART0_BASE) / (UART1_BASE - UART0_BASE); \
am_hal_pwrctrl_periph_e eUARTPowerModule = \
((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + module)); \
return am_hal_pwrctrl_periph_enable(eUARTPowerModule); \
} \
static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
{ \
return clk_enable_ambiq_uart(dev, clk); \
}
#else
#define DEVPWRSTATUS_OFFSET 0x4
#define AMBIQ_UART_DEFINE(n) \
PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \
static int pwr_on_ambiq_uart_##n(void) \
{ \
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET; \
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) != \
DT_INST_PHA(n, ambiq_pwrcfg, mask)) { \
}; \
return 0; \
} \
static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
{ \
return clk_enable_ambiq_uart(dev, clk); \
}
#endif
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */

8
dts/arm/ambiq/ambiq_apollo3_blue.dtsi
View file

@ -90,12 +90,6 @@
};
};
pwrcfg: pwrcfg@40021000 {
compatible = "ambiq,pwrctrl";
reg = <0x40021000 0x400>;
#pwrcfg-cells = <2>;
};
stimer0: stimer@40008140 {
compatible = "ambiq,stimer";
reg = <0x40008140 0x80>;
@ -182,7 +176,6 @@
interrupt-names = "UART0";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
zephyr,pm-device-runtime-auto;
};
@ -193,7 +186,6 @@
interrupt-names = "UART1";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
zephyr,pm-device-runtime-auto;
};

8
dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
View file

@ -108,12 +108,6 @@
};
};
pwrcfg: pwrcfg@40021000 {
compatible = "ambiq,pwrctrl";
reg = <0x40021000 0x400>;
#pwrcfg-cells = <2>;
};
stimer0: stimer@40008140 {
compatible = "ambiq,stimer";
reg = <0x40008140 0x80>;
@ -200,7 +194,6 @@
interrupt-names = "UART0";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
zephyr,pm-device-runtime-auto;
};
@ -211,7 +204,6 @@
interrupt-names = "UART1";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
zephyr,pm-device-runtime-auto;
};

10
dts/arm/ambiq/ambiq_apollo4p.dtsi
View file

@ -92,12 +92,6 @@
};
};
pwrcfg: pwrcfg@40021000 {
compatible = "ambiq,pwrctrl";
reg = <0x40021000 0x400>;
#pwrcfg-cells = <2>;
};
stimer0: stimer@40008800 {
compatible = "ambiq,stimer";
reg = <0x40008800 0x80>;
@ -121,7 +115,6 @@
interrupt-names = "UART0";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
};
uart1: uart@4001d000 {
@ -131,7 +124,6 @@
interrupt-names = "UART1";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
};
uart2: uart@4001e000 {
@ -141,7 +133,6 @@
interrupt-names = "UART2";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
};
uart3: uart@4001f000 {
@ -151,7 +142,6 @@
interrupt-names = "UART3";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
};
iom0: iom@40050000 {

10
dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
View file

@ -73,12 +73,6 @@
};
};
pwrcfg: pwrcfg@40021000 {
compatible = "ambiq,pwrctrl";
reg = <0x40021000 0x400>;
#pwrcfg-cells = <2>;
};
stimer0: stimer@40008800 {
compatible = "ambiq,stimer";
reg = <0x40008800 0x80>;
@ -102,7 +96,6 @@
interrupt-names = "UART0";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
};
uart1: uart@4001d000 {
compatible = "ambiq,uart", "arm,pl011";
@ -111,7 +104,6 @@
interrupt-names = "UART1";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
};
uart2: uart@4001e000 {
@ -121,7 +113,6 @@
interrupt-names = "UART2";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
};
uart3: uart@4001f000 {
@ -131,7 +122,6 @@
interrupt-names = "UART3";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
};
iom0: iom@40050000 {

10
dts/arm/ambiq/ambiq_apollo510.dtsi
View file

@ -118,12 +118,6 @@
soc {
compatible = "ambiq,apollo510", "ambiq,apollo5x", "simple-bus";
pwrcfg: pwrcfg@PWRCTRL_BASE_NAME {
compatible = "ambiq,pwrctrl";
reg = <PWRCTRL_REG_BASE PWRCTRL_REG_SIZE>;
#pwrcfg-cells = <2>;
};
stimer0: stimer@STIMER_BASE_NAME {
compatible = "ambiq,stimer";
reg = <STIMER_REG_BASE STIMER_REG_SIZE>;
@ -146,7 +140,6 @@
interrupt-names = "UART0";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
};
uart1: uart@UART1_BASE_NAME {
@ -156,7 +149,6 @@
interrupt-names = "UART1";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
};
uart2: uart@UART2_BASE_NAME {
@ -166,7 +158,6 @@
interrupt-names = "UART2";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
};
uart3: uart@UART3_BASE_NAME {
@ -176,7 +167,6 @@
interrupt-names = "UART3";
status = "disabled";
clocks = <&uartclk>;
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
};
pinctrl: pin-controller@GPIO_BASE_NAME {

22
dts/bindings/power/ambiq,pwrctrl.yaml
View file

@ -1,22 +0,0 @@
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
description: Ambiq power control
compatible: "ambiq,pwrctrl"
include: base.yaml
properties:
reg:
required: true
"#pwrcfg-cells":
type: int
required: true
const: 2
description: Number of items to expect in a power configuration
pwrcfg-cells:
- offset
- mask

11
dts/bindings/power/ambiq-pwrcfg.yaml
View file

@ -1,11 +0,0 @@
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
description: Ambiq peripheral power configuration
properties:
ambiq,pwrcfg:
type: phandle-array
specifier-space: pwrcfg
description: Power configuration

5
dts/bindings/serial/ambiq,uart.yaml
View file

@ -5,7 +5,7 @@ description: Ambiq UART controller (PL011 compatible)
compatible: "ambiq,uart"
include: ["arm,pl011.yaml", pinctrl-device.yaml, ambiq-pwrcfg.yaml]
include: ["arm,pl011.yaml", pinctrl-device.yaml]
properties:
pinctrl-0:
@ -13,6 +13,3 @@ properties:
pinctrl-names:
required: true
ambiq,pwrcfg:
required: true