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arm: Cortex-M0: Adapt core register code to M0

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The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.

Jira: ZEP-1497

Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Carles Cufi 2016-12-28 17:47:14 +01:00 • committed by Anas Nashif
commit b6109496ff
5 changed files with 174 additions and 133 deletions
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2
arch/arm/core/cortex_m/scb.c
View file

@ -90,6 +90,7 @@ void sys_arch_reboot(int type)
DO_REBOOT();
}
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
/**
*
* @brief Set the number of priority groups based on the number of exception
@ -134,3 +135,4 @@ void _ScbNumPriGroupSet(unsigned int n)
__scs.scb.aircr.val = reg.val;
}
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */

2
arch/arm/core/fault.c
View file

@ -376,5 +376,7 @@ void _Fault(const NANO_ESF *esf)
*/
void _FaultInit(void)
{
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
_ScbDivByZeroFaultEnable();
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
}