From b53c6c1fe351d5b75ce1e9689d4928cefb4ee6a3 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 12 Nov 2018 22:19:27 +0100 Subject: [PATCH] soc: same70: enable instruction cache on sam_e70 The Cortex-M7 CPU included in the SAM e70 SoCs has an instruction cache that significantly boost the performances. Enable it during the SoC initialization. Signed-off-by: Aurelien Jarno --- soc/arm/atmel_sam/same70/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c index 86ed0d10b3b..13625b02bef 100644 --- a/soc/arm/atmel_sam/same70/soc.c +++ b/soc/arm/atmel_sam/same70/soc.c @@ -227,6 +227,8 @@ static int atmel_same70_init(struct device *arg) key = irq_lock(); + SCB_EnableICache(); + /* Clear all faults */ _ClearFaults();