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soc: intel_adsp: Unbreak older cAVS devices

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On pre-2.5 cAVS, the initial IDC interrupt to start the other core is
handled by software in the firmware ROM.  That means that it has to be
unmasked for the mechanism to work (with 2.5, the interrupt is handled
by hardware regardless of what the masking state in the interrupt
controller is).

Similarly, the Xtensa Region Protection Option entries have already
been set by ROM code when we arrive in enable_l1_cache(), so we can
skip that part on older machines.  Also removed because trying to
rewrite those entries was causing inexplicable hangs on cAVS 1.5,
plausibly because the region had active cache lines.

(This patch is separate for easier review in a long evolving PR.
Technically it represents a bisection problem as the "New IDC Driver"
patch before this was a regression.  Seems like a safe enough thing to
handle if you land on this.)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-08-30 20:25:07 -07:00 • committed by Anas Nashif
commit b53af38f7a
1 changed files with 6 additions and 0 deletions
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6
soc/xtensa/intel_adsp/common/soc_mp.c
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@ -186,12 +186,15 @@ static ALWAYS_INLINE void enable_l1_cache(void)
* hardware register), but it generates significantly larger
* code.
*/
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V25
/* Already set up by the ROM on older hardware. */
const uint8_t attribs[] = { 2, 15, 15, 15, 2, 4, 15, 15 };
for (int region = 0; region < 8; region++) {
reg = 0x20000000 * region;
__asm__ volatile("wdtlb %0, %1" :: "r"(attribs[region]), "r"(reg));
}
#endif
}
void z_mp_entry(void)
@ -332,6 +335,9 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
z_mp_stack_top = Z_THREAD_STACK_BUFFER(stack) + sz;
/* Pre-2.x cAVS delivers the IDC to ROM code, so unmask it */
CAVS_INTCTRL[cpu_num].l2.clear = CAVS_L2_IDC;
/* Disable automatic power and clock gating for that CPU, so
* it won't just go back to sleep. Note that after startup,
* the cores are NOT power gated even if they're configured to