boards: ambiq: apollo3: add connector dtsi for apollo3 boards
Added connector dtsi files for apollo3_evb and apollo3p_evb, and ran gpio_basic_api to test, all cases pass Signed-off-by: Hao Luo <hluo@ambiq.com>
This commit is contained in:
Hao Luo
Carles Cufí
parent
02af64400f
commit
b532a3ea7f
8 changed files with 212 additions and 3 deletions
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@ -5,6 +5,7 @@
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*/
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*/
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#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
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#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
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#include "apollo3_evb_connector.dtsi"
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&pinctrl {
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&pinctrl {
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uart0_default: uart0_default {
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uart0_default: uart0_default {
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67
boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi
Normal file
67
boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi
Normal file
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@ -0,0 +1,67 @@
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/*
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* Copyright (c) 2024 Ambiq <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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ambiq_header: connector {
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compatible = "ambiq-header";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffff80>;
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gpio-map-pass-thru = <0 0x7f>;
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gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL */
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<1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA */
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<2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */
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<3 0 &gpio0_31 3 0>, /* IOS_CE */
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<4 0 &gpio0_31 4 0>, /* IOS_INT */
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<5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */
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<6 0 &gpio0_31 6 0>, /* IOM0_SPI_MISO, IOM0_I2C_SDA */
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<7 0 &gpio0_31 7 0>, /* IOM0_SPI_MOSI */
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<8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */
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<9 0 &gpio0_31 9 0>, /* IOM1_SPI_MISO, IOM1_I2C_SDA */
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<10 0 &gpio0_31 10 0>, /* LED0, IOM1_SPI_MOSI */
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<11 0 &gpio0_31 11 0>, /* DISP_RESET */
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<12 0 &gpio0_31 12 0>, /* MSPI0_CE0 */
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<13 0 &gpio0_31 13 0>, /* IOM0_CS */
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<14 0 &gpio0_31 14 0>, /* LED3 */
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<15 0 &gpio0_31 15 0>, /* LED2 */
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<16 0 &gpio0_31 16 0>, /* BUTTON0 */
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<17 0 &gpio0_31 17 0>, /* LED4 */
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<18 0 &gpio0_31 18 0>, /* BUTTON1 */
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<19 0 &gpio0_31 19 0>, /* BUTTON2 */
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<20 0 &gpio0_31 20 0>, /* SWDCK */
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<21 0 &gpio0_31 21 0>, /* SWDIO */
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<22 0 &gpio0_31 22 0>, /* MSPI0_D0, UART0_TX */
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<23 0 &gpio0_31 23 0>, /* MSPI0_D3, UART0_RX */
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<24 0 &gpio0_31 24 0>, /* MSPI0_SCK */
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<25 0 &gpio0_31 25 0>, /* IOM2_MISO_SCK, IOM2_I2C_SDA */
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<26 0 &gpio0_31 26 0>, /* MSPI0_D1 */
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<27 0 &gpio0_31 27 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL*/
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<28 0 &gpio0_31 28 0>, /* MSPI0_CE0 */
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<29 0 &gpio0_31 29 0>, /* IOM3_CS */
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<30 0 &gpio0_31 30 0>, /* LED1 */
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<31 0 &gpio0_31 31 0>, /* DISP_3V3_EN */
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<32 0 &gpio32_63 0 0>, /* BLEIF_MOSI */
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<33 0 &gpio32_63 1 0>, /* BLEIF_CSN */
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<34 0 &gpio32_63 2 0>, /* IOM1_CS */
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<35 0 &gpio32_63 3 0>, /* BLEIF_STATUS */
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<36 0 &gpio32_63 4 0>, /* PDM_DATA */
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<37 0 &gpio32_63 5 0>, /* PDM_CLK */
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<38 0 &gpio32_63 6 0>, /* DISP_TE */
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<39 0 &gpio32_63 7 0>, /* DISP_PWR_EN */
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<40 0 &gpio32_63 8 0>, /* IOM4_SPI_MISO, IOM4_I2C_SDA */
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<41 0 &gpio32_63 9 0>, /* SWO */
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<42 0 &gpio32_63 10 0>, /* IOM3_I2C_SCL */
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<43 0 &gpio32_63 11 0>, /* IOM3_I2C_SDA */
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<44 0 &gpio32_63 12 0>, /* IOM4_SPI_MOSI */
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<45 0 &gpio32_63 13 0>, /* DISP_2V8_EN */
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<46 0 &gpio32_63 14 0>, /* ACC_INT */
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<47 0 &gpio32_63 15 0>, /* IOM5_SPI_MOSI */
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<48 0 &gpio32_63 16 0>, /* IOM5_I2C_SCL */
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<49 0 &gpio32_63 17 0>; /* IOM5_I2C_SDA */
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};
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};
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ambiq_spi0: &spi0 {};
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ambiq_i2c3: &i2c3 {};
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@ -5,6 +5,7 @@
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*/
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*/
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#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
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#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
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#include "apollo3p_evb_connector.dtsi"
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&pinctrl {
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&pinctrl {
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uart0_default: uart0_default {
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uart0_default: uart0_default {
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92
boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi
Normal file
92
boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi
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@ -0,0 +1,92 @@
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/*
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* Copyright (c) 2024 Ambiq <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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ambiq_header: connector {
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compatible = "ambiq-header";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffff80>;
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gpio-map-pass-thru = <0 0x7f>;
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gpio-map = <0 0 &gpio0_31 0 0>, /* IOS_SPI_SCK, IOS_I2C_SCL */
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<1 0 &gpio0_31 1 0>, /* IOS_SPI_MOSI, IOS_I2C_SDA */
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<2 0 &gpio0_31 2 0>, /* IOS_SPI_MISO */
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<3 0 &gpio0_31 3 0>, /* IOS_CE */
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<4 0 &gpio0_31 4 0>, /* IOS_INT */
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<5 0 &gpio0_31 5 0>, /* IOM0_SPI_SCK, IOM0_I2C_SCL */
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<6 0 &gpio0_31 6 0>, /* IOM0_SPI_MISO, IOM0_I2C_SDA */
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<7 0 &gpio0_31 7 0>, /* IOM0_SPI_MOSI */
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<8 0 &gpio0_31 8 0>, /* IOM1_SPI_SCK, IOM1_I2C_SCL */
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<9 0 &gpio0_31 9 0>, /* IOM1_SPI_MISO, IOM1_I2C_SDA */
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<10 0 &gpio0_31 10 0>, /* LED0, IOM1_SPI_MOSI */
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<11 0 &gpio0_31 11 0>, /* DISP_RESET */
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<12 0 &gpio0_31 12 0>, /* MSPI0_CE0 */
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<13 0 &gpio0_31 13 0>, /* IOM0_CS */
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<14 0 &gpio0_31 14 0>, /* LED3 */
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<15 0 &gpio0_31 15 0>, /* LED2 */
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<16 0 &gpio0_31 16 0>, /* BUTTON0 */
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<17 0 &gpio0_31 17 0>, /* LED4 */
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<18 0 &gpio0_31 18 0>, /* BUTTON1 */
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<19 0 &gpio0_31 19 0>, /* BUTTON2 */
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<20 0 &gpio0_31 20 0>, /* SWDCK */
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<21 0 &gpio0_31 21 0>, /* SWDIO */
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<22 0 &gpio0_31 22 0>, /* MSPI0_D0, UART0_TX */
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<23 0 &gpio0_31 23 0>, /* MSPI0_D3, UART0_RX */
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<24 0 &gpio0_31 24 0>, /* MSPI0_SCK */
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<25 0 &gpio0_31 25 0>, /* IOM2_MISO_SCK, IOM2_I2C_SDA */
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<26 0 &gpio0_31 26 0>, /* MSPI0_D1 */
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<27 0 &gpio0_31 27 0>, /* IOM2_SPI_SCK, IOM2_I2C_SCL*/
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<28 0 &gpio0_31 28 0>, /* MSPI0_CE0 */
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<29 0 &gpio0_31 29 0>, /* IOM3_CS */
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<30 0 &gpio0_31 30 0>, /* LED1 */
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<31 0 &gpio0_31 31 0>, /* DISP_3V3_EN */
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<32 0 &gpio32_63 0 0>, /* BLEIF_MOSI */
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<33 0 &gpio32_63 1 0>, /* BLEIF_CSN */
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<34 0 &gpio32_63 2 0>, /* IOM1_CS */
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<35 0 &gpio32_63 3 0>, /* BLEIF_STATUS */
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<36 0 &gpio32_63 4 0>, /* PDM_DATA */
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<37 0 &gpio32_63 5 0>, /* PDM_CLK */
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<38 0 &gpio32_63 6 0>, /* DISP_TE */
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<39 0 &gpio32_63 7 0>, /* DISP_PWR_EN */
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<40 0 &gpio32_63 8 0>, /* IOM4_SPI_MISO, IOM4_I2C_SDA */
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<41 0 &gpio32_63 9 0>, /* SWO */
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<42 0 &gpio32_63 10 0>, /* IOM3_I2C_SCL */
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<43 0 &gpio32_63 11 0>, /* IOM3_I2C_SDA */
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<44 0 &gpio32_63 12 0>, /* IOM4_SPI_MOSI */
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<45 0 &gpio32_63 13 0>, /* DISP_2V8_EN */
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<46 0 &gpio32_63 14 0>, /* ACC_INT */
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<47 0 &gpio32_63 15 0>, /* IOM5_SPI_MOSI */
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<48 0 &gpio32_63 16 0>, /* IOM5_I2C_SCL */
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<49 0 &gpio32_63 17 0>, /* IOM5_I2C_SDA */
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<50 0 &gpio32_63 18 0>, /* MSPI1_CE0 */
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<51 0 &gpio32_63 19 0>, /* MSPI1_D0 */
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<52 0 &gpio32_63 20 0>, /* MSPI1_D1 */
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<53 0 &gpio32_63 21 0>, /* MSPI1_D2 */
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<54 0 &gpio32_63 22 0>, /* MSPI1_D3 */
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<55 0 &gpio32_63 23 0>, /* MSPI1_D4 */
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<56 0 &gpio32_63 24 0>, /* MSPI1_D5 */
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<57 0 &gpio32_63 25 0>, /* MSPI1_D6 */
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<58 0 &gpio32_63 26 0>, /* MSPI1_D7 */
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<59 0 &gpio32_63 27 0>, /* MSPI1_SCK */
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<60 0 &gpio32_63 28 0>, /* MSPI1_DMDQS */
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<61 0 &gpio32_63 29 0>, /* MSPI2_CE1 */
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<62 0 &gpio32_63 30 0>, /* MSPI1_CE1 */
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<63 0 &gpio32_63 31 0>, /* MSPI2_CE0 */
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<64 0 &gpio64_95 0 0>, /* MSPI2_D0 */
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<65 0 &gpio64_95 1 0>, /* MSPI2_D1 */
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<66 0 &gpio64_95 2 0>, /* MSPI2_D2 */
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<67 0 &gpio64_95 3 0>, /* MSPI2_D3 */
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<68 0 &gpio64_95 4 0>, /* MSPI0_SCK */
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<69 0 &gpio64_95 5 0>, /* MSPI1_CE0 */
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<70 0 &gpio64_95 6 0>, /* See am_hal_pins.h file for further info */
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<71 0 &gpio64_95 7 0>, /* See am_hal_pins.h file for further info */
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<72 0 &gpio64_95 8 0>, /* See am_hal_pins.h file for further info */
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<73 0 &gpio64_95 9 0>, /* See am_hal_pins.h file for further info */
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<74 0 &gpio64_95 10 0>; /* See am_hal_pins.h file for further info */
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};
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};
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ambiq_spi0: &spi0 {};
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ambiq_i2c3: &i2c3 {};
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@ -36,6 +36,7 @@ struct ambiq_gpio_data {
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static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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static int ambiq_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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{
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const struct ambiq_gpio_config *const dev_cfg = dev->config;
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const struct ambiq_gpio_config *const dev_cfg = dev->config;
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int ret;
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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#if defined(CONFIG_SOC_SERIES_APOLLO3X)
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pin += dev_cfg->offset;
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pin += dev_cfg->offset;
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am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR);
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am_hal_gpio_state_write(pin, AM_HAL_GPIO_OUTPUT_CLEAR);
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}
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}
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#endif
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#endif
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am_hal_gpio_pinconfig(pin, pincfg);
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return 0;
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if (am_hal_gpio_pinconfig(pin, pincfg) != AM_HAL_STATUS_SUCCESS) {
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ret = -ENOTSUP;
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}
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return ret;
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}
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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#ifdef CONFIG_GPIO_GET_CONFIG
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&counter0 {
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status = "okay";
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};
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&counter1 {
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status = "disabled";
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};
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&counter2 {
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status = "disabled";
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};
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&counter3 {
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status = "disabled";
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};
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&counter4 {
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status = "disabled";
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};
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&counter5 {
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status = "disabled";
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};
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&counter6 {
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status = "disabled";
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};
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&counter7 {
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status = "disabled";
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};
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@ -977,7 +977,7 @@ static bool reliable_cancel_capable(const struct device *dev)
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}
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}
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#endif
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#endif
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#ifdef CONFIG_COUNTER_AMBIQ
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#ifdef CONFIG_COUNTER_AMBIQ
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if (dev == DEVICE_DT_GET(DT_NODELABEL(counter0))) {
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if (single_channel_alarm_capable(dev)) {
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return true;
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return true;
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}
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}
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#endif
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#endif
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13
tests/drivers/gpio/gpio_basic_api/boards/apollo3_evb.overlay
Normal file
13
tests/drivers/gpio/gpio_basic_api/boards/apollo3_evb.overlay
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/*
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* Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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resources {
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compatible = "test-gpio-basic-api";
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out-gpios = <&ambiq_header 5 0>;
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in-gpios = <&ambiq_header 6 0>;
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};
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};
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