diff --git a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst index 82f37189c45..ab518ee5784 100644 --- a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst +++ b/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst @@ -168,6 +168,8 @@ features: +===========+============+=====================================+ | NVIC | on-chip | nested vector interrupt controller | +-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: ``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`` diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml index 6f401eb2d19..639b2fa4965 100644 --- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml +++ b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml @@ -6,6 +6,8 @@ toolchain: - zephyr - gccarmemb - xtools +supported: + - gpio testing: ignore_tags: - cmsis_rtos_v2 @@ -17,7 +19,6 @@ testing: - cmm - shell - LED - - gpio - nfc ram: 256 flash: 64 diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig index 5b498e3c74d..5066a9a5d44 100644 --- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig +++ b/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig @@ -6,6 +6,9 @@ CONFIG_CORTEX_M_SYSTICK=y # 209 MHz system clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000 +# enable GPIO +CONFIG_GPIO=y + # clock configuration CONFIG_CLOCK_CONTROL=y diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 067765f6fec..7e870816006 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -214,6 +214,8 @@ const int gpio_stm32_enable_int(int port, int pin) #if defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32F0X) line = ((pin % 4 * 4) << 16) | (pin / 4); +#elif defined(CONFIG_SOC_SERIES_STM32MP1X) + line = (((pin * 8) % 32) << 16) | (pin / 4); #else line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4); #endif @@ -231,6 +233,8 @@ const int gpio_stm32_enable_int(int port, int pin) #ifdef CONFIG_SOC_SERIES_STM32F1X LL_GPIO_AF_SetEXTISource(port, line); +#elif CONFIG_SOC_SERIES_STM32MP1X + LL_EXTI_SetEXTISource(port, line); #else LL_SYSCFG_SetEXTISource(port, line); #endif diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h index 74133824333..970d9c68667 100644 --- a/drivers/gpio/gpio_stm32.h +++ b/drivers/gpio/gpio_stm32.h @@ -112,6 +112,19 @@ #define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG #define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH #define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI +#elif CONFIG_SOC_SERIES_STM32MP1X +#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4 +#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA +#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB +#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC +#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD +#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE +#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF +#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG +#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH +#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI +#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ +#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK #elif CONFIG_SOC_SERIES_STM32WBX #define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2 #define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi index 13e511bff1f..36dba666b1d 100644 --- a/dts/arm/st/mp1/stm32mp157.dtsi +++ b/dts/arm/st/mp1/stm32mp157.dtsi @@ -6,6 +6,8 @@ #include #include +#include +#include / { cpus { @@ -39,6 +41,111 @@ label = "STM32_CLK_RCC"; }; + pinctrl: pin-controller@50002000 { + compatible = "st,stm32-pinmux"; + reg = <0x50002000 0x9000>; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@50002000 { + compatible = "st,stm32-gpio"; + reg = <0x50002000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>; + label = "GPIOA"; + }; + + gpiob: gpio@50003000 { + compatible = "st,stm32-gpio"; + reg = <0x50003000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>; + label = "GPIOB"; + }; + + gpioc: gpio@50004000 { + compatible = "st,stm32-gpio"; + reg = <0x50004000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>; + label = "GPIOC"; + }; + + gpiod: gpio@50005000 { + compatible = "st,stm32-gpio"; + reg = <0x50005000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>; + label = "GPIOD"; + }; + + gpioe: gpio@50006000 { + compatible = "st,stm32-gpio"; + reg = <0x50006000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>; + label = "GPIOE"; + }; + + gpiof: gpio@50007000 { + compatible = "st,stm32-gpio"; + reg = <0x50007000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>; + label = "GPIOF"; + }; + + gpiog: gpio@50008000 { + compatible = "st,stm32-gpio"; + reg = <0x50008000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>; + label = "GPIOG"; + }; + + gpioh: gpio@50009000 { + compatible = "st,stm32-gpio"; + reg = <0x50009000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>; + label = "GPIOH"; + }; + + gpioi: gpio@5000a000 { + compatible = "st,stm32-gpio"; + reg = <0x5000a000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>; + label = "GPIOI"; + }; + + gpioj: gpio@5000b000 { + compatible = "st,stm32-gpio"; + reg = <0x5000b000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>; + label = "GPIOJ"; + }; + + gpiok: gpio@5000c000 { + compatible = "st,stm32-gpio"; + reg = <0x5000c000 0x400>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>; + label = "GPIOK"; + }; + }; }; }; diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series index 4f843ee4fbd..2dc3d722376 100644 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series +++ b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series @@ -16,4 +16,32 @@ config STM32_CORE_CM4 bool "define stm32 core" default y +if GPIO_STM32 + +config GPIO_STM32_PORTD + default y + +config GPIO_STM32_PORTE + default y + +config GPIO_STM32_PORTF + default y + +config GPIO_STM32_PORTG + default y + +config GPIO_STM32_PORTH + default y + +config GPIO_STM32_PORTI + default y + +config GPIO_STM32_PORTJ + default y + +config GPIO_STM32_PORTK + default y + +endif # GPIO_STM32 + endif # SOC_SERIES_STM32MP1X diff --git a/soc/arm/st_stm32/stm32mp1/dts_fixup.h b/soc/arm/st_stm32/stm32mp1/dts_fixup.h index 668704a3efd..51eb1eb3c6c 100644 --- a/soc/arm/st_stm32/stm32mp1/dts_fixup.h +++ b/soc/arm/st_stm32/stm32mp1/dts_fixup.h @@ -8,4 +8,190 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50002000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50002000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50002000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50002000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL \ + DT_ST_STM32_GPIO_50002000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE \ + DT_ST_STM32_GPIO_50002000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS \ + DT_ST_STM32_GPIO_50002000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS \ + DT_ST_STM32_GPIO_50002000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50003000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50003000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50003000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50003000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL \ + DT_ST_STM32_GPIO_50003000_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE \ + DT_ST_STM32_GPIO_50003000_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS \ + DT_ST_STM32_GPIO_50003000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS \ + DT_ST_STM32_GPIO_50003000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50004000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50004000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50004000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50004000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL \ + DT_ST_STM32_GPIO_50004000_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE \ + DT_ST_STM32_GPIO_50004000_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS \ + DT_ST_STM32_GPIO_50004000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS \ + DT_ST_STM32_GPIO_50004000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50005000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50005000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 \ + T_ST_STM32_GPIO_50005000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50005000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL \ + DT_ST_STM32_GPIO_50005000_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE \ + DT_ST_STM32_GPIO_50005000_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS \ + DT_ST_STM32_GPIO_50005000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS \ + DT_ST_STM32_GPIO_50005000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50006000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50006000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50006000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50006000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL \ + DT_ST_STM32_GPIO_50006000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE \ + DT_ST_STM32_GPIO_50006000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS \ + DT_ST_STM32_GPIO_50006000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS \ + DT_ST_STM32_GPIO_50006000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50007000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50007000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50007000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50007000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL \ + DT_ST_STM32_GPIO_50007000_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE \ + DT_ST_STM32_GPIO_50007000_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS \ + DT_ST_STM32_GPIO_50007000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS \ + DT_ST_STM32_GPIO_50007000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50008000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50008000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50008000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50008000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL \ + DT_ST_STM32_GPIO_50008000_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE \ + DT_ST_STM32_GPIO_50008000_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS \ + DT_ST_STM32_GPIO_50008000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS \ + DT_ST_STM32_GPIO_50008000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS \ + DT_ST_STM32_GPIO_50009000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_50009000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_50009000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_50009000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL \ + DT_ST_STM32_GPIO_50009000_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE \ + DT_ST_STM32_GPIO_50009000_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS \ + DT_ST_STM32_GPIO_50009000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS \ + DT_ST_STM32_GPIO_50009000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS \ + DT_ST_STM32_GPIO_5000A000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_5000A000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_5000A000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_5000A000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOI_LABEL \ + DT_ST_STM32_GPIO_5000A000_LABEL +#define DT_GPIO_STM32_GPIOI_SIZE \ + DT_ST_STM32_GPIO_5000A000_SIZE +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS \ + DT_ST_STM32_GPIO_5000A000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS \ + DT_ST_STM32_GPIO_5000A000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOJ_BASE_ADDRESS \ + DT_ST_STM32_GPIO_5000B000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_5000B000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_5000B000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_5000B000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOJ_LABEL \ + DT_ST_STM32_GPIO_5000B000_LABEL +#define DT_GPIO_STM32_GPIOJ_SIZE \ + DT_ST_STM32_GPIO_5000B000_SIZE +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS \ + DT_ST_STM32_GPIO_5000B000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS \ + DT_ST_STM32_GPIO_5000B000_CLOCK_BUS + +#define DT_GPIO_STM32_GPIOK_BASE_ADDRESS \ + DT_ST_STM32_GPIO_5000C000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS_0 \ + DT_ST_STM32_GPIO_5000C000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS_0 \ + DT_ST_STM32_GPIO_5000C000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_CONTROLLER \ + DT_ST_STM32_GPIO_5000C000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOK_LABEL \ + DT_ST_STM32_GPIO_5000C000_LABEL +#define DT_GPIO_STM32_GPIOK_SIZE \ + DT_ST_STM32_GPIO_5000C000_SIZE +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS \ + DT_ST_STM32_GPIO_5000C000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS \ + DT_ST_STM32_GPIO_5000C000_CLOCK_BUS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32mp1/soc.h b/soc/arm/st_stm32/stm32mp1/soc.h index f605b84b6b9..7ac56bcfabe 100644 --- a/soc/arm/st_stm32/stm32mp1/soc.h +++ b/soc/arm/st_stm32/stm32mp1/soc.h @@ -31,6 +31,10 @@ #include #endif +#ifdef CONFIG_GPIO_STM32 +#include +#endif + #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE #include #include