diff --git a/arch/arm/core/cortex_m/mpu/Kconfig b/arch/arm/core/cortex_m/mpu/Kconfig index 64d71af4d48..711a3279f02 100644 --- a/arch/arm/core/cortex_m/mpu/Kconfig +++ b/arch/arm/core/cortex_m/mpu/Kconfig @@ -24,7 +24,7 @@ config MPU_STACK_GUARD config ARM_MPU bool "ARM MPU Support" depends on CPU_HAS_MPU - depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32 + depends on SOC_FAMILY_ARM || SOC_FAMILY_STM32 || SOC_FAMILY_NRF5 select ARM_CORE_MPU default n help diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series index d2e462ecbf0..85a669178af 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series +++ b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series @@ -10,6 +10,7 @@ config SOC_SERIES_NRF52X select CPU_CORTEX_M select CPU_CORTEX_M4 select CPU_HAS_FPU + select CPU_HAS_MPU select SOC_FAMILY_NRF5 select NRF_RTC_TIMER select CLOCK_CONTROL diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc index 3f1f73736e1..a4f6ea76eb2 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc +++ b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc @@ -26,3 +26,11 @@ config SOC_NRF52840_QIAA select SOC_NRF52840 endchoice + +config ARM_MPU_NRF52X + bool "Enable MPU on nRF52" + depends on CPU_HAS_MPU + select ARM_MPU + default n + help + Enable MPU support on Nordic Semiconductor nRF52x series ICs. diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Makefile b/arch/arm/soc/nordic_nrf5/nrf52/Makefile index 5ca1d7c5573..8ad96799ff0 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Makefile +++ b/arch/arm/soc/nordic_nrf5/nrf52/Makefile @@ -10,6 +10,7 @@ soc-cflags += -DNRF52840_XXAA endif obj-y += soc.o +obj-$(CONFIG_ARM_MPU_NRF52X) += mpu_regions.o zephyr: $(KERNEL_HEX_NAME) all: $(KERNEL_HEX_NAME) diff --git a/arch/arm/soc/nordic_nrf5/nrf52/mpu_mem_cfg.h b/arch/arm/soc/nordic_nrf5/nrf52/mpu_mem_cfg.h new file mode 100644 index 00000000000..cd456f84f65 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf52/mpu_mem_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _NRF52X_MPU_MEM_CFG_H_ +#define _NRF52X_MPU_MEM_CFG_H_ + +#include +#include + +/* Flash Region Definitions */ +#if CONFIG_FLASH_SIZE == 64 +#define REGION_FLASH_SIZE REGION_64K +#elif CONFIG_FLASH_SIZE == 128 +#define REGION_FLASH_SIZE REGION_128K +#elif CONFIG_FLASH_SIZE == 256 +#define REGION_FLASH_SIZE REGION_256K +#elif CONFIG_FLASH_SIZE == 512 +#define REGION_FLASH_SIZE REGION_512K +#elif CONFIG_FLASH_SIZE == 1024 +#define REGION_FLASH_SIZE REGION_1M +#elif CONFIG_FLASH_SIZE == 2048 +#define REGION_FLASH_SIZE REGION_2M +#else +#error "Unsupported configuration" +#endif + +/* SRAM Region Definitions */ +#if CONFIG_SRAM_SIZE == 32 +#define REGION_SRAM_0_SIZE REGION_32K +#elif CONFIG_SRAM_SIZE == 64 +#define REGION_SRAM_0_SIZE REGION_64K +#elif CONFIG_SRAM_SIZE == 128 +#define REGION_SRAM_0_SIZE REGION_128K +#elif CONFIG_SRAM_SIZE == 256 +#define REGION_SRAM_0_SIZE REGION_256K +#else +#error "Unsupported configuration" +#endif + +#endif /* _NRF52X_MPU_MEM_CFG_H_ */ diff --git a/arch/arm/soc/nordic_nrf5/nrf52/mpu_regions.c b/arch/arm/soc/nordic_nrf5/nrf52/mpu_regions.c new file mode 100644 index 00000000000..da4b0f98b58 --- /dev/null +++ b/arch/arm/soc/nordic_nrf5/nrf52/mpu_regions.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "mpu_mem_cfg.h" + +#define XICR_BASE 0x10000000 +#define PERIPH_BASE 0x40000000 +#define M4_PPB_BASE 0xE0000000 + +static struct arm_mpu_region mpu_regions[] = { + /* Region 0 */ + MPU_REGION_ENTRY("FLASH_0", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_ATTR(REGION_FLASH_SIZE)), + /* Region 1 */ + MPU_REGION_ENTRY("SRAM_0", + CONFIG_SRAM_BASE_ADDRESS, + REGION_RAM_ATTR(REGION_SRAM_0_SIZE)), + /* Region 2 */ + MPU_REGION_ENTRY("FACTUSERCFG_0", + XICR_BASE, + REGION_IO_ATTR(REGION_8K)), + /* Region 3 */ + MPU_REGION_ENTRY("PERIPH_0", + PERIPH_BASE, + REGION_IO_ATTR(REGION_512M)), + /* Region 4 */ + MPU_REGION_ENTRY("PPB_0", + M4_PPB_BASE, + REGION_PPB_ATTR(REGION_64K)), +}; + +struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig b/boards/arm/96b_nitrogen/96b_nitrogen_defconfig index 11612ee6513..fb027a1d692 100644 --- a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig +++ b/boards/arm/96b_nitrogen/96b_nitrogen_defconfig @@ -3,6 +3,9 @@ CONFIG_SOC_FAMILY_NRF5=y CONFIG_SOC_SERIES_NRF52X=y CONFIG_BOARD_96B_NITROGEN=y +# Enable MPU +CONFIG_ARM_MPU_NRF52X=y + # enable uart driver CONFIG_SERIAL=y CONFIG_UART_NRF5=y diff --git a/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig b/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig index 9ae816a6e18..3578fe73ed8 100644 --- a/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig +++ b/boards/arm/nrf52840_pca10056/nrf52840_pca10056_defconfig @@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y CONFIG_SOC_NRF52840_QIAA=y CONFIG_BOARD_NRF52840_PCA10056=y +# Enable MPU +CONFIG_ARM_MPU_NRF52X=y + # enable uart driver CONFIG_SERIAL=y CONFIG_UART_NRF5=y diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig index 71fe9bd1a39..aed60ff7080 100644 --- a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig +++ b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig @@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y CONFIG_SOC_NRF52832_QFAA=y CONFIG_BOARD_NRF52_BLENANO2=y +# Enable MPU +CONFIG_ARM_MPU_NRF52X=y + # enable uart driver CONFIG_SERIAL=y CONFIG_UART_NRF5=y diff --git a/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig b/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig index c8519fe923c..1a87f5654f0 100644 --- a/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig +++ b/boards/arm/nrf52_pca10040/nrf52_pca10040_defconfig @@ -4,6 +4,9 @@ CONFIG_SOC_SERIES_NRF52X=y CONFIG_SOC_NRF52832_QFAA=y CONFIG_BOARD_NRF52_PCA10040=y +# Enable MPU +CONFIG_ARM_MPU_NRF52X=y + # enable uart driver CONFIG_SERIAL=y CONFIG_UART_NRF5=y