arch/x86: apollo_lake: add PCI related bits for UARTs/I2Cs
This adds PCI related configuration for UARTs and I2C controllers to the Apollo Lake SoC configuration to support PCI devices. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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bcc95235c5
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3 changed files with 176 additions and 1 deletions
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@ -22,7 +22,7 @@ config CLFLUSH_DETECT
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if UART_NS16550
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config UART_NS16550_PCI
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def_bool n
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def_bool y if PCI
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config UART_NS16550_PORT_0
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def_bool y
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@ -32,6 +32,9 @@ if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_OPTIONS
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default 0
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config UART_NS16550_PORT_0_PCI
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def_bool y if PCI
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endif # UART_NS16550_PORT_0
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config UART_NS16550_PORT_1
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@ -42,8 +45,31 @@ if UART_NS16550_PORT_1
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config UART_NS16550_PORT_1_OPTIONS
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default 0
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config UART_NS16550_PORT_1_PCI
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def_bool y if PCI
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endif # UART_NS16550_PORT_1
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if UART_NS16550_PORT_2
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config UART_NS16550_PORT_2_OPTIONS
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default 0
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config UART_NS16550_PORT_2_PCI
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def_bool y if PCI
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endif # UART_NS16550_PORT_2
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if UART_NS16550_PORT_3
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config UART_NS16550_PORT_3_OPTIONS
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default 0
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config UART_NS16550_PORT_3_PCI
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def_bool y if PCI
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endif # UART_NS16550_PORT_3
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endif # UART_NS16550
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endif # SOC_APOLLO_LAKE
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@ -43,6 +43,16 @@ MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_2
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#ifdef CONFIG_UART_NS16550_PORT_3
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MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_3_BASE_ADDR, 0x1000,
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(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
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#endif
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#endif /* CONFIG_UART_NS16550 */
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/* for I2C controllers */
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@ -23,4 +23,143 @@
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#include <random/rand32.h>
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#endif
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#ifdef CONFIG_PCI
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/*
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* PCI definitions
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*/
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#define PCI_BUS_NUMBERS 1
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#define PCI_CTRL_ADDR_REG 0xCF8
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#define PCI_CTRL_DATA_REG 0xCFC
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/**
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* @brief Convert PCI interrupt PIN to IRQ
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*
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* BIOS should have assigned vectors linearly.
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* If not, override this in board configuration.
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*/
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#define pci_pin2irq(bus, dev, pin) (pin)
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/* UARTs */
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#ifdef CONFIG_UART_NS16550_PCI
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#ifdef CONFIG_UART_NS16550_PORT_0_PCI
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#define UART_NS16550_PORT_0_PCI_CLASS 0x11
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#define UART_NS16550_PORT_0_PCI_BUS 0
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#define UART_NS16550_PORT_0_PCI_DEV 18
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#define UART_NS16550_PORT_0_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_0_PCI_DEVICE_ID 0x5abc
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#define UART_NS16550_PORT_0_PCI_FUNC 0
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#define UART_NS16550_PORT_0_PCI_BAR 0
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#endif /* CONFIG_UART_NS16550_PORT_0_PCI */
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#ifdef CONFIG_UART_NS16550_PORT_1_PCI
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#define UART_NS16550_PORT_1_PCI_CLASS 0x11
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#define UART_NS16550_PORT_1_PCI_BUS 0
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#define UART_NS16550_PORT_1_PCI_DEV 18
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#define UART_NS16550_PORT_1_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_1_PCI_DEVICE_ID 0x5abe
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#define UART_NS16550_PORT_1_PCI_FUNC 1
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#define UART_NS16550_PORT_1_PCI_BAR 0
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#endif /* CONFIG_UART_NS16550_PORT_1_PCI */
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#ifdef CONFIG_UART_NS16550_PORT_2_PCI
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#define UART_NS16550_PORT_2_PCI_CLASS 0x11
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#define UART_NS16550_PORT_2_PCI_BUS 0
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#define UART_NS16550_PORT_2_PCI_DEV 18
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#define UART_NS16550_PORT_2_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_2_PCI_DEVICE_ID 0x5ac0
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#define UART_NS16550_PORT_2_PCI_FUNC 2
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#define UART_NS16550_PORT_2_PCI_BAR 0
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#endif /* CONFIG_UART_NS16550_PORT_2_PCI */
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#ifdef CONFIG_UART_NS16550_PORT_3_PCI
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#define UART_NS16550_PORT_3_PCI_CLASS 0x11
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#define UART_NS16550_PORT_3_PCI_BUS 0
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#define UART_NS16550_PORT_3_PCI_DEV 18
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#define UART_NS16550_PORT_3_PCI_VENDOR_ID 0x8086
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#define UART_NS16550_PORT_3_PCI_DEVICE_ID 0x5aee
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#define UART_NS16550_PORT_3_PCI_FUNC 3
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#define UART_NS16550_PORT_3_PCI_BAR 0
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#endif /* CONFIG_UART_NS16550_PORT_3_PCI */
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#endif /* CONFIG_UART_NS16550_PCI */
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/* I2C controllers */
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#define I2C_DW_0_PCI_VENDOR_ID 0x8086
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#define I2C_DW_0_PCI_DEVICE_ID 0x5aac
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#define I2C_DW_0_PCI_CLASS 0x11
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#define I2C_DW_0_PCI_BUS 0
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#define I2C_DW_0_PCI_DEV 16
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#define I2C_DW_0_PCI_FUNCTION 0
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#define I2C_DW_0_PCI_BAR 0
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#define I2C_DW_1_PCI_VENDOR_ID 0x8086
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#define I2C_DW_1_PCI_DEVICE_ID 0x5aae
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#define I2C_DW_1_PCI_CLASS 0x11
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#define I2C_DW_1_PCI_BUS 0
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#define I2C_DW_1_PCI_DEV 16
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#define I2C_DW_1_PCI_FUNCTION 1
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#define I2C_DW_1_PCI_BAR 0
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#define I2C_DW_2_PCI_VENDOR_ID 0x8086
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#define I2C_DW_2_PCI_DEVICE_ID 0x5ab0
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#define I2C_DW_2_PCI_CLASS 0x11
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#define I2C_DW_2_PCI_BUS 0
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#define I2C_DW_2_PCI_DEV 16
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#define I2C_DW_2_PCI_FUNCTION 2
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#define I2C_DW_2_PCI_BAR 0
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#define I2C_DW_3_PCI_VENDOR_ID 0x8086
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#define I2C_DW_3_PCI_DEVICE_ID 0x5ab2
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#define I2C_DW_3_PCI_CLASS 0x11
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#define I2C_DW_3_PCI_BUS 0
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#define I2C_DW_3_PCI_DEV 16
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#define I2C_DW_3_PCI_FUNCTION 3
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#define I2C_DW_3_PCI_BAR 0
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#define I2C_DW_4_PCI_VENDOR_ID 0x8086
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#define I2C_DW_4_PCI_DEVICE_ID 0x5ab4
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#define I2C_DW_4_PCI_CLASS 0x11
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#define I2C_DW_4_PCI_BUS 0
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#define I2C_DW_4_PCI_DEV 17
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#define I2C_DW_4_PCI_FUNCTION 0
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#define I2C_DW_4_PCI_BAR 0
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#define I2C_DW_5_PCI_VENDOR_ID 0x8086
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#define I2C_DW_5_PCI_DEVICE_ID 0x5ab6
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#define I2C_DW_5_PCI_CLASS 0x11
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#define I2C_DW_5_PCI_BUS 0
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#define I2C_DW_5_PCI_DEV 17
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#define I2C_DW_5_PCI_FUNCTION 1
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#define I2C_DW_5_PCI_BAR 0
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#define I2C_DW_6_PCI_VENDOR_ID 0x8086
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#define I2C_DW_6_PCI_DEVICE_ID 0x5ab8
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#define I2C_DW_6_PCI_CLASS 0x11
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#define I2C_DW_6_PCI_BUS 0
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#define I2C_DW_6_PCI_DEV 17
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#define I2C_DW_6_PCI_FUNCTION 2
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#define I2C_DW_6_PCI_BAR 0
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#define I2C_DW_7_PCI_VENDOR_ID 0x8086
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#define I2C_DW_7_PCI_DEVICE_ID 0x5aba
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#define I2C_DW_7_PCI_CLASS 0x11
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#define I2C_DW_7_PCI_BUS 0
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#define I2C_DW_7_PCI_DEV 17
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#define I2C_DW_7_PCI_FUNCTION 3
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#define I2C_DW_7_PCI_BAR 0
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#endif /* CONFIG_PCI */
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#endif /* __SOC_H_ */
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