From b3c46083fb07b579ecfb46decc32fd2c5ecd6a45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kim=20B=C3=B8ndergaard?= Date: Tue, 13 Jun 2023 15:13:56 +0200 Subject: [PATCH] drivers: rtc: stm32: New stm32 RTC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit STM32 RTC driver for the new RTC API. Can't coexist with old COUNTER based RTC Though supported by HW, RTC_ALARM still to be supported by driver Signed-off-by: Kim Bøndergaard --- drivers/rtc/CMakeLists.txt | 1 + drivers/rtc/Kconfig | 1 + drivers/rtc/Kconfig.stm32 | 12 ++ drivers/rtc/rtc_ll_stm32.c | 170 ++++++++++++++++++ .../rtc/rtc_api/boards/nucleo_h563zi.overlay | 11 ++ 5 files changed, 195 insertions(+) create mode 100644 drivers/rtc/Kconfig.stm32 create mode 100644 drivers/rtc/rtc_ll_stm32.c create mode 100644 tests/drivers/rtc/rtc_api/boards/nucleo_h563zi.overlay diff --git a/drivers/rtc/CMakeLists.txt b/drivers/rtc/CMakeLists.txt index 267347fc664..3f07a859da1 100644 --- a/drivers/rtc/CMakeLists.txt +++ b/drivers/rtc/CMakeLists.txt @@ -10,3 +10,4 @@ zephyr_library_sources_ifdef(CONFIG_RTC_EMUL rtc_emul.c) zephyr_library_sources_ifdef(CONFIG_RTC_PCF8523 rtc_pcf8523.c) zephyr_library_sources_ifdef(CONFIG_RTC_PCF8563 rtc_pcf8563.c) zephyr_library_sources_ifdef(CONFIG_RTC_MOTOROLA_MC146818 rtc_mc146818.c) +zephyr_library_sources_ifdef(CONFIG_RTC_STM32 rtc_ll_stm32.c) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 25e135438bc..e2f0a43bf52 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -39,5 +39,6 @@ source "drivers/rtc/Kconfig.emul" source "drivers/rtc/Kconfig.pcf8523" source "drivers/rtc/Kconfig.pcf8563" source "drivers/rtc/Kconfig.mc146818" +source "drivers/rtc/Kconfig.stm32" endif # RTC diff --git a/drivers/rtc/Kconfig.stm32 b/drivers/rtc/Kconfig.stm32 new file mode 100644 index 00000000000..510d259a206 --- /dev/null +++ b/drivers/rtc/Kconfig.stm32 @@ -0,0 +1,12 @@ +# Copyright 2023 Prevas A/S +# SPDX-License-Identifier: Apache-2.0 + +config RTC_STM32 + bool "STM32 RTC driver" + default y if !COUNTER + depends on DT_HAS_ST_STM32_RTC_ENABLED + select USE_STM32_LL_RTC + select USE_STM32_LL_PWR + select USE_STM32_LL_RCC + help + Build RTC driver for STM32 SoCs. diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c new file mode 100644 index 00000000000..7380fb102fa --- /dev/null +++ b/drivers/rtc/rtc_ll_stm32.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2023 Prevas A/S + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#define DT_DRV_COMPAT st_stm32_rtc + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL); + +/* Convert calendar start time */ +/* RTC start time: 1st, Jan, 2000 */ +/* struct tm start: 1st, Jan, 1900 */ +#define TM_TO_RTC_OFFSET 100 + +struct rtc_stm32_config { + LL_RTC_InitTypeDef ll_rtc_config; + const struct stm32_pclken *pclken; +}; + +struct rtc_stm32_data { + /* Currently empty */ +}; + +static int rtc_stm32_init(const struct device *dev) +{ + const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); + const struct rtc_stm32_config *cfg = dev->config; + + if (!device_is_ready(clk)) { + LOG_ERR("clock control device not ready"); + return -ENODEV; + } + + /* Enable RTC bus clock */ + if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]) != 0) { + LOG_ERR("clock op failed\n"); + return -EIO; + } + + /* Enable Backup access */ + z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); +#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP) + LL_PWR_EnableBkUpAccess(); +#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */ + + /* Enable RTC clock source */ + if (clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL) != 0) { + LOG_ERR("clock configure failed\n"); + return -EIO; + } + + LL_RCC_EnableRTC(); + + z_stm32_hsem_unlock(CFG_HW_RCC_SEMID); + + if (LL_RTC_Init(RTC, ((LL_RTC_InitTypeDef *)&cfg->ll_rtc_config)) != SUCCESS) { + return -EIO; + } + +#ifdef RTC_CR_BYPSHAD + LL_RTC_DisableWriteProtection(RTC); + LL_RTC_EnableShadowRegBypass(RTC); + LL_RTC_EnableWriteProtection(RTC); +#endif /* RTC_CR_BYPSHAD */ + + return 0; +} + +static const struct stm32_pclken rtc_clk[] = STM32_DT_INST_CLOCKS(0); + +static const struct rtc_stm32_config rtc_config = { + .ll_rtc_config = { + .HourFormat = LL_RTC_HOURFORMAT_24HOUR, +#if DT_INST_CLOCKS_CELL(1, bus) == STM32_SRC_LSI + /* prescaler values for LSI @ 32 KHz */ + .AsynchPrescaler = 0x7F, + .SynchPrescaler = 0x00F9, +#else /* DT_INST_CLOCKS_CELL(1, bus) == STM32_SRC_LSE */ + /* prescaler values for LSE @ 32768 Hz */ + .AsynchPrescaler = 0x7F, + .SynchPrescaler = 0x00FF, +#endif + }, + .pclken = rtc_clk, +}; + +static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *timeptr) +{ + LOG_INF("Setting clock"); + LL_RTC_DisableWriteProtection(RTC); + + LL_RTC_EnableInitMode(RTC); + + while (!LL_RTC_IsActiveFlag_INIT(RTC)) { + }; + + LL_RTC_DATE_SetYear(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_year - TM_TO_RTC_OFFSET)); + LL_RTC_DATE_SetMonth(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_mon + 1)); + LL_RTC_DATE_SetDay(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_mday)); + + LL_RTC_DATE_SetWeekDay(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_wday) + 1); + + LL_RTC_TIME_SetHour(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_hour)); + LL_RTC_TIME_SetMinute(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_min)); + LL_RTC_TIME_SetSecond(RTC, __LL_RTC_CONVERT_BIN2BCD(timeptr->tm_sec)); + + LL_RTC_DisableInitMode(RTC); + + LL_RTC_EnableWriteProtection(RTC); + + return 0; +} + +static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr) +{ + ARG_UNUSED(dev); + + uint32_t rtc_date, rtc_time; + + /* Read time and date registers */ + rtc_time = LL_RTC_TIME_Get(RTC); + rtc_date = LL_RTC_DATE_Get(RTC); + + timeptr->tm_year = TM_TO_RTC_OFFSET + __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_YEAR(rtc_date)); + /* tm_mon allowed values are 0-11 */ + timeptr->tm_mon = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_MONTH(rtc_date)) - 1; + timeptr->tm_mday = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_DAY(rtc_date)); + timeptr->tm_wday = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_WEEKDAY(rtc_date)) - 1; + + timeptr->tm_hour = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_HOUR(rtc_time)); + timeptr->tm_min = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_MINUTE(rtc_time)); + timeptr->tm_sec = __LL_RTC_CONVERT_BCD2BIN(__LL_RTC_GET_SECOND(rtc_time)); + + timeptr->tm_nsec = LL_RTC_TIME_GetSubSecond(RTC); + + return 0; +} + +struct rtc_driver_api rtc_stm32_driver_api = { + .set_time = rtc_stm32_set_time, + .get_time = rtc_stm32_get_time, + /* RTC_ALARM not supported */ + /* RTC_UPDATE not supported */ +}; + +#define RTC_STM32_DEV_CFG(n) \ + static struct rtc_stm32_data rtc_data_##n = {}; \ + \ + DEVICE_DT_INST_DEFINE(n, &rtc_stm32_init, NULL, &rtc_data_##n, &rtc_config, POST_KERNEL, \ + CONFIG_RTC_INIT_PRIORITY, &rtc_stm32_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(RTC_STM32_DEV_CFG); diff --git a/tests/drivers/rtc/rtc_api/boards/nucleo_h563zi.overlay b/tests/drivers/rtc/rtc_api/boards/nucleo_h563zi.overlay new file mode 100644 index 00000000000..6b78b2a9a57 --- /dev/null +++ b/tests/drivers/rtc/rtc_api/boards/nucleo_h563zi.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Prevas A/S + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + rtc = &rtc; + }; +};