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boards: frdm_mcxn947: Add a variant for executing from QSPI

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1. The boards always boots from internal flash. However it does
have an external QSPI that can be used to store Zephyr.
Add a variant to support running Zephyr from QSPI Flash.
Running Zephyr from QSPI requires a bootloader like MCUboot
to be pogrammed to internal flash.
2. Create a common dts file to add features that are enabled for
CPU 0 that is included by both vairants i.e internal flash (default)
and QSPI variant.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2024-04-24 13:43:24 -05:00 • committed by Anas Nashif
commit b32a86ad8d
8 changed files with 313 additions and 172 deletions
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2
boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947
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@ -2,6 +2,6 @@
# SPDX-License-Identifier: Apache-2.0
config BOARD_FRDM_MCXN947
select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0
select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0 || BOARD_FRDM_MCXN947_MCXN947_CPU0_QSPI
select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1
select SOC_PART_NUMBER_MCXN947VDF

3
boards/nxp/frdm_mcxn947/board.yml
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@ -3,3 +3,6 @@ board:
vendor: nxp
socs:
- name: mcxn947
variants:
- name: qspi
cpucluster: 'cpu0'

36
boards/nxp/frdm_mcxn947/doc/index.rst
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@ -205,6 +205,42 @@ see the following message in the terminal:
*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0
Flashing to QSPI
================
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: zephyr/samples/hello_world -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" -DCONFIG_BOOTLOADER_MCUBOOT=y
:board: frdm_mcxn947/mcxn947/cpu0/qspi
:goals: flash
In order to load Zephyr application from QSPI you should program a bootloader like
MCUboot bootloader to internal flash. Here are the steps.
.. zephyr-app-commands::
:zephyr-app: bootloader/mcuboot/boot/zephyr
:board: frdm_mcxn947/mcxn947/cpu0/qspi
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting MCUboot v2.1.0-rc1-2-g9f034729d99a ***
*** Using Zephyr OS build v3.6.0-4046-gf279a03af8ab ***
I: Starting bootloader
I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
I: Boot source: none
I: Image index: 0, Swap type: none
I: Bootloader chainload address offset: 0x0
I: Jumping to the first image slot
*** Booting Zephyr OS build v3.6.0-4046-gf279a03af8ab ***
Hello World! frdm_mcxn947/mcxn947/cpu0/qspi
Debugging
=========

172
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts
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@ -6,179 +6,9 @@
/dts-v1/;
#include <nxp/nxp_mcxn94x.dtsi>
#include "frdm_mcxn947.dtsi"
#include "frdm_mcxn947_mcxn947_cpu0.dtsi"
/ {
model = "NXP FRDM_N94 board";
compatible = "nxp,mcxn947", "nxp,mcx";
cpus {
/delete-node/ cpu@1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash;
zephyr,flash-controller = &fmu;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm4_lpuart4;
zephyr,shell-uart = &flexcomm4_lpuart4;
zephyr,canbus = &flexcan0;
};
aliases{
watchdog0 = &wwdt0;
pwm-0 = &flexpwm1_pwm0;
};
};
/*
* Default for this board is to allocate SRAM0-5 to cpu0 but the
* application can have an application specific device tree to
* allocate the SRAM0-7 differently.
*
* For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
* for cpu1. This would require the value of sram0 to have a DT_SIZE_K
* of 384. You would have to make updates to cpu1 sram settings as well.
*/
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(320)>;
};
&gpio4 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&edma0 {
status = "okay";
};
&flexcomm1 {
status = "okay";
};
&flexcomm1_lpspi1 {
status = "okay";
};
&flexcomm2 {
status = "okay";
};
&flexcomm2_lpi2c2 {
status = "okay";
};
/*
*LPFLEXCOMM supports UART and I2C on the same instance, enable this for
* LFLEXCOMM2
*/
&flexcomm2_lpuart2 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&flexcomm4_lpuart4 {
status = "okay";
};
&flexspi {
status = "okay";
};
&w25q64jvssiq {
status = "okay";
};
&dac0 {
status = "okay";
};
&enet {
status = "okay";
};
&enet_mac {
status = "okay";
};
&enet_mdio {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&flexpwm1_pwm0 {
status = "okay";
};
&flexcan0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};
&usdhc0 {
status = "okay";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&vref {
status = "okay";
};
&lpadc0 {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&lpcmp0 {
status = "okay";
};
&lptmr0 {
status = "okay";
};
&flexio0 {
status = "okay";
};

185
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi Normal file
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@ -0,0 +1,185 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Common dts file to enable supported features for CPU 0.
* This file is included by both the default variant
* which is run from internal flash and the QSPI variant.
*/
/dts-v1/;
#include <nxp/nxp_mcxn94x.dtsi>
#include "frdm_mcxn947.dtsi"
/ {
cpus {
/delete-node/ cpu@1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash;
zephyr,flash-controller = &fmu;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm4_lpuart4;
zephyr,shell-uart = &flexcomm4_lpuart4;
zephyr,canbus = &flexcan0;
};
aliases{
watchdog0 = &wwdt0;
pwm-0 = &flexpwm1_pwm0;
};
};
/*
* Default for this board is to allocate SRAM0-5 to cpu0 but the
* application can have an application specific device tree to
* allocate the SRAM0-7 differently.
*
* For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
* for cpu1. This would require the value of sram0 to have a DT_SIZE_K
* of 384. You would have to make updates to cpu1 sram settings as well.
*/
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(320)>;
};
&gpio4 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&edma0 {
status = "okay";
};
&flexcomm1 {
status = "okay";
};
&flexcomm1_lpspi1 {
status = "okay";
};
&flexcomm2 {
status = "okay";
};
&flexcomm2_lpi2c2 {
status = "okay";
};
/*
*LPFLEXCOMM supports UART and I2C on the same instance, enable this for
* LFLEXCOMM2
*/
&flexcomm2_lpuart2 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&flexcomm4_lpuart4 {
status = "okay";
};
&flexspi {
status = "okay";
};
&w25q64jvssiq {
status = "okay";
};
&dac0 {
status = "okay";
};
&enet {
status = "okay";
};
&enet_mac {
status = "okay";
};
&enet_mdio {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&flexpwm1_pwm0 {
status = "okay";
};
&flexcan0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};
&usdhc0 {
status = "okay";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&vref {
status = "okay";
};
&lpadc0 {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&lpcmp0 {
status = "okay";
};
&lptmr0 {
status = "okay";
};
&flexio0 {
status = "okay";
};

44
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.dts Normal file
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@ -0,0 +1,44 @@
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "frdm_mcxn947_mcxn947_cpu0.dtsi"
/delete-node/ &slot0_partition;
/delete-node/ &slot1_partition;
/delete-node/ &storage_partition;
/ {
model = "NXP FRDM_N94 board, QSPI variant";
compatible = "nxp,mcxn947", "nxp,mcx";
chosen {
zephyr,flash = &w25q64jvssiq;
};
};
&w25q64jvssiq {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 DT_SIZE_M(3)>;
};
slot1_partition: partition@300000 {
label = "image-1";
reg = <0x00300000 DT_SIZE_M(3)>;
};
storage_partition: partition@600000 {
label = "storage";
reg = <0x00600000 DT_SIZE_M(2)>;
};
};
};

25
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml Normal file
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@ -0,0 +1,25 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
identifier: frdm_mcxn947/mcxn947/cpu0/qspi
name: NXP FRDM MCXN947 QSPI (CPU0)
type: mcu
arch: arm
ram: 320
flash: 8192
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- dma
- gpio
- watchdog
- pwm
- counter
- sdhc
- usb_device
vendor: nxp

18
boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig Normal file
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@ -0,0 +1,18 @@
#
# Copyright 2024 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y