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ext: stm32cube: update stm32l4xx cube version

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Update Cube version for STM32L4XX family
from version: V1.10.0
to version: V1.12.0

This version solves patch in drivers/include/stm32l4xx_ll_spi.h

Note: git shows 100% diff on all files.
You need to tick "Ignore space change" in git UI to see real
differences. I tried different things to fix this without
success (dos2unix, file encoding, files access right).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2018-06-27 16:53:28 +02:00 • committed by Kumar Gala
commit b3127629c7
230 changed files with 638806 additions and 621060 deletions
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16
ext/hal/st/stm32cube/stm32l4xx/README
View file

@ -6,7 +6,7 @@ Origin:
http://www.st.com/en/embedded-software/stm32cubel4.html http://www.st.com/en/embedded-software/stm32cubel4.html
Status: Status:
version 1.10.0 version 1.12.0
Purpose: Purpose:
ST Microelectronics official MCU package for STM32L4 series. ST Microelectronics official MCU package for STM32L4 series.
@ -23,7 +23,7 @@ URL:
http://www.st.com/en/embedded-software/stm32cubel4.html http://www.st.com/en/embedded-software/stm32cubel4.html
commit: commit:
version 1.10.0 version 1.12.0
Maintained-by: Maintained-by:
External External
@ -36,18 +36,6 @@ License Link:
Patch List: Patch List:
*Current implementation of LL_SPI_TransmitData16 on F3/F7/L4 family
generates following warning:
"warning: dereferencing type-punned pointer will break strict-aliasing
rules [-Wstrict-aliasing]"
Besides being forbidden by rule, this cast is not needed, as register is
16 bits wide. Modification has been tested on L4 SoC.
stm32yyxx_ll_spi.h being included in soc.h file, warning is generated
at each compiled object, this commit allows a clean build.
Impacted files:
drivers/include/stm32l4xx_ll_spi.h
ST Bug tracker ID: 13359
* The STM32L4x2 SoCs need to control the isolation of the USB features * The STM32L4x2 SoCs need to control the isolation of the USB features
from VDDUSB. This is done through the PWR_CR2 bit USV. The STM32L4 HAL from VDDUSB. This is done through the PWR_CR2 bit USV. The STM32L4 HAL
in stm32l4xx_ll_pwr.h wrongly checks for the PWR_CR2_PVME1 bit, which in stm32l4xx_ll_pwr.h wrongly checks for the PWR_CR2_PVME1 bit, which

246
ext/hal/st/stm32cube/stm32l4xx/drivers/include/Legacy/stm32_hal_legacy.h
View file

@ -35,8 +35,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_HAL_LEGACY #ifndef STM32_HAL_LEGACY
#define __STM32_HAL_LEGACY #define STM32_HAL_LEGACY
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -274,7 +274,96 @@
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
#if defined(STM32L4)
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32L4 */
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32H7 */
/** /**
* @} * @}
@ -355,6 +444,30 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif
/**
* @}
*/
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7 */
/** /**
* @} * @}
@ -431,12 +544,12 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -456,78 +569,6 @@
* @} * @}
*/ */
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@ -887,6 +928,10 @@
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
#if defined(STM32L0)
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
#endif
/** /**
* @} * @}
*/ */
@ -1047,8 +1092,8 @@
* @} * @}
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@ -2119,6 +2164,21 @@
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
#if defined(STM32WB)
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
#define QSPI_IRQHandler QUADSPI_IRQHandler
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@ -2787,7 +2847,9 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32WB) || defined(STM32G0) #if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif #endif
@ -3038,6 +3100,16 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif #endif
#if defined(STM32H7)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
#endif
/** /**
* @} * @}
*/ */
@ -3226,7 +3298,10 @@
* @{ * @{
*/ */
#define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_LAYER LTDC_LAYER
#if defined(STM32F7)
#else
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
#endif
/** /**
* @} * @}
*/ */
@ -3252,6 +3327,17 @@
* @} * @}
*/ */
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
#endif
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{ * @{
@ -3265,7 +3351,7 @@
} }
#endif #endif
#endif /* ___STM32_HAL_LEGACY */ #endif /* STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

769
ext/hal/st/stm32cube/stm32l4xx/drivers/include/Legacy/stm32l4xx_hal_can_legacy.h Normal file
View file

@ -0,0 +1,769 @@
/**
******************************************************************************
* @file stm32l4xx_hal_can_legacy.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_CAN_LEGACY_H
#define __STM32L4xx_CAN_LEGACY_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(CAN1)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
}HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE */
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE */
}CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE */
uint32_t BankNumber; /*!< Select the start slave bank filter.
This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
}CAN_FilterConfTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
}CanTxMsgTypeDef;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
}CanRxMsgTypeDef;
/**
* @brief CAN handle Structure definition
*/
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
HAL_LockTypeDef Lock; /*!< CAN locking object */
__IO uint32_t ErrorCode; /*!< CAN Error code */
}CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */
#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */
#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */
#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */
#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */
#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN initialization Status
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_interrupts CAN Interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/* Mailboxes definition */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macro CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state.
* @param __HANDLE__: CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupt.
* @param __HANDLE__: CAN handle.
* @param __INTERRUPT__: CAN Interrupt.
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupt.
* @param __HANDLE__: CAN handle.
* @param __INTERRUPT__: CAN Interrupt.
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/**
* @brief Return the number of pending received messages.
* @param __HANDLE__: CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__: specifies the CAN Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
/** @brief Check whether the specified CAN interrupt source is enabled or not.
* @param __HANDLE__: specifies the CAN Handle.
* @param __INTERRUPT__: specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Check the transmission status of a CAN Frame.
* @param __HANDLE__: specifies the CAN Handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
* @retval The new status of transmission (TRUE or FALSE).
*/
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__: CAN handle.
* @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
* @param __HANDLE__: specifies the CAN Handle.
* @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
* @retval None
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
/**
* @brief Enable or disable the DBG Freeze for CAN.
* @param __HANDLE__: specifies the CAN Handle.
* @param __NEWSTATE__: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFO can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* addtogroup and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
/** @defgroup CAN_transmit_constants CAN Transmit Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
/**
* @}
*/
#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* CAN1 */
#ifdef __cplusplus
}
#endif
#endif /* __STM32L4xx_HAL_CAN_LEGACY_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

87
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_adc.h
View file

@ -364,23 +364,56 @@ typedef struct
/** /**
* @brief ADC handle Structure definition * @brief ADC handle Structure definition
*/ */
typedef struct typedef struct __ADC_HandleTypeDef
{ {
ADC_TypeDef *Instance; /*!< Register base address */ ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */ HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */ __IO uint32_t ErrorCode; /*!< ADC Error code */
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef; }ADC_HandleTypeDef;
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL ADC Callback ID enumeration definition
*/
typedef enum
{
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
} HAL_ADC_CallbackIDTypeDef;
/**
* @brief HAL ADC Callback pointer definition
*/
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -401,6 +434,9 @@ typedef struct
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -689,17 +725,17 @@ typedef struct
/** @defgroup ADC_interrupts_definition ADC interrupts definition /** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{ * @{
*/ */
#define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready interrupt source */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
#define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
#define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
#define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
#define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
@ -1026,8 +1062,17 @@ typedef struct
* @param __HANDLE__ ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
#endif
/** /**
* @brief Enable ADC interrupt. * @brief Enable ADC interrupt.
@ -1698,6 +1743,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

762
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_can.h
View file

File diff suppressed because it is too large Load diff

68
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_comp.h
View file

@ -41,8 +41,6 @@
extern "C" { extern "C" {
#endif #endif
#if defined (COMP1) || defined (COMP2)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
#include "stm32l4xx_ll_exti.h" #include "stm32l4xx_ll_exti.h"
@ -50,6 +48,7 @@
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
#if defined (COMP1) || defined (COMP2)
/** @addtogroup COMP /** @addtogroup COMP
* @{ * @{
@ -113,14 +112,38 @@ typedef enum
/** /**
* @brief COMP Handle Structure definition * @brief COMP Handle Structure definition
*/ */
typedef struct typedef struct __COMP_HandleTypeDef
{ {
COMP_TypeDef *Instance; /*!< Register base address */ COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */ COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
__IO uint32_t ErrorCode; /*!< COMP error code */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} COMP_HandleTypeDef; } COMP_HandleTypeDef;
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL COMP Callback ID enumeration definition
*/
typedef enum
{
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
} HAL_COMP_CallbackIDTypeDef;
/**
* @brief HAL COMP Callback pointer definition
*/
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -130,6 +153,17 @@ typedef struct
* @{ * @{
*/ */
/** @defgroup COMP_Error_Code COMP Error Code
* @{
*/
#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup COMP_WindowMode COMP Window Mode /** @defgroup COMP_WindowMode COMP Window Mode
* @{ * @{
*/ */
@ -192,7 +226,7 @@ typedef struct
#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */ #define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ #define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ #define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST) /*!< Hysteresis level high */ #define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
/** /**
* @} * @}
*/ */
@ -268,7 +302,22 @@ typedef struct
* @param __HANDLE__ COMP handle * @param __HANDLE__ COMP handle
* @retval None * @retval None
*/ */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
#endif
/**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/** /**
* @brief Enable the specified comparator. * @brief Enable the specified comparator.
@ -667,6 +716,12 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -699,6 +754,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
* @{ * @{
*/ */
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/** /**
* @} * @}
*/ */
@ -710,7 +766,7 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
/** /**
* @} * @}
*/ */
#endif /* COMP1 || COMP2 */
/** /**
* @} * @}
*/ */
@ -719,8 +775,6 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
} }
#endif #endif
#endif /* COMP1 || COMP2 */
#endif /* __STM32L4xx_HAL_COMP_H */ #endif /* __STM32L4xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

73
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_conf.h
View file

@ -53,6 +53,7 @@
#define HAL_MODULE_ENABLED #define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_COMP_MODULE_ENABLED #define HAL_COMP_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED
@ -106,11 +107,11 @@
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
@ -118,7 +119,7 @@
* This value is the default MSI range value after Reset. * This value is the default MSI range value after Reset.
*/ */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
/** /**
@ -127,7 +128,7 @@
* (when HSI is used as system clock source, directly or through the PLL). * (when HSI is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
@ -138,7 +139,7 @@
* which is subject to manufacturing process variations. * which is subject to manufacturing process variations.
*/ */
#if !defined (HSI48_VALUE) #if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/ The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */ #endif /* HSI48_VALUE */
@ -146,7 +147,7 @@
* @brief Internal Low Speed oscillator (LSI) value. * @brief Internal Low Speed oscillator (LSI) value.
*/ */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature.*/ in voltage and temperature.*/
@ -155,11 +156,11 @@
* This value is used by the UART, RTC HAL module to compute the system frequency * This value is used by the UART, RTC HAL module to compute the system frequency
*/ */
#if !defined (LSE_VALUE) #if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT) #if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
@ -168,7 +169,7 @@
* frequency. * frequency.
*/ */
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/ #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/** /**
@ -177,7 +178,7 @@
* frequency. * frequency.
*/ */
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/ #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,
@ -187,8 +188,8 @@
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 0U #define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U
@ -201,6 +202,50 @@
*/ */
/* #define USE_FULL_ASSERT 1U */ /* #define USE_FULL_ASSERT 1U */
/* ################## Register callback feature configuration ############### */
/**
* @brief Set below the peripheral configuration to "1U" to add the support
* of HAL callback registration/deregistration feature for the HAL
* driver(s). This allows user application to provide specific callback
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
* the default weak callback functions (see each stm32l4xx_hal_ppp.h file
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
* for each PPP peripheral).
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
#define USE_HAL_SD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U
#define USE_HAL_UART_REGISTER_CALLBACKS 0U
#define USE_HAL_USART_REGISTER_CALLBACKS 0U
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
@ -243,6 +288,10 @@
#include "stm32l4xx_hal_can.h" #include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */ #endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "Legacy/stm32l4xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED #ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h" #include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */ #endif /* HAL_COMP_MODULE_ENABLED */

36
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cortex.h
View file

@ -287,40 +287,6 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void); void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
#if (__MPU_PRESENT == 1)
/**
* @brief Disable the MPU.
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Disable(void)
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
#endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
@ -341,6 +307,8 @@ void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void); void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**

50
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_crc.h
View file

@ -53,7 +53,6 @@
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types /** @defgroup CRC_Exported_Types CRC Exported Types
* @{ * @{
*/ */
@ -63,15 +62,13 @@
*/ */
typedef enum typedef enum
{ {
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef; } HAL_CRC_StateTypeDef;
/** /**
* @brief CRC Init Structure definition * @brief CRC Init Structure definition
*/ */
@ -116,8 +113,6 @@ typedef struct
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
} CRC_InitTypeDef; } CRC_InitTypeDef;
/** /**
* @brief CRC Handle Structure definition * @brief CRC Handle Structure definition
*/ */
@ -140,8 +135,6 @@ typedef struct
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
must occur if InputBufferFormat is not one of the three values listed above */ must occur if InputBufferFormat is not one of the three values listed above */
} CRC_HandleTypeDef; } CRC_HandleTypeDef;
/** /**
* @} * @}
*/ */
@ -188,10 +181,10 @@ typedef struct
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP /** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{ * @{
*/ */
#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */ #define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B (CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */ #define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B (CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */ #define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */ #define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/** /**
* @} * @}
*/ */
@ -235,45 +228,46 @@ typedef struct
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros /** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{ * @{
*/ */
/** @brief Reset CRC handle state. /** @brief Reset CRC handle state.
* @param __HANDLE__: CRC handle. * @param __HANDLE__ CRC handle.
* @retval None * @retval None
*/ */
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/** /**
* @brief Reset CRC Data Register. * @brief Reset CRC Data Register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval None * @retval None
*/ */
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/** /**
* @brief Set CRC INIT non-default value * @brief Set CRC INIT non-default value
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @param __INIT__: 32-bit initial value * @param __INIT__ 32-bit initial value
* @retval None * @retval None
*/ */
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/** /**
* @brief Store a 8-bit data in the Independent Data(ID) register. * @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @param __VALUE__: 8-bit value to be stored in the ID register * @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None * @retval None
*/ */
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/** /**
* @brief Return the 8-bit data stored in the Independent Data(ID) register. * @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval 8-bit value of the ID register * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/ */
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/** /**
@ -282,7 +276,7 @@ typedef struct
/* Private macros --------------------------------------------------------*/ /* Private macros --------------------------------------------------------*/
/** @addtogroup CRC_Private_Macros CRC Private Macros /** @defgroup CRC_Private_Macros CRC Private Macros
* @{ * @{
*/ */

32
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_crc_ex.h
View file

@ -54,17 +54,17 @@
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants /** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{ * @{
*/ */
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes /** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{ * @{
*/ */
#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */ #define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE (CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD (CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD (CRC_CR_REV_IN) /*!< Word-wise input data inversion */ #define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/** /**
* @} * @}
*/ */
@ -72,8 +72,8 @@
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes /** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{ * @{
*/ */
#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */ #define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE (CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */ #define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/** /**
* @} * @}
*/ */
@ -83,28 +83,28 @@
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros /** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{ * @{
*/ */
/** /**
* @brief Set CRC output reversal * @brief Set CRC output reversal
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval None * @retval None
*/ */
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) #define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/** /**
* @brief Unset CRC output reversal * @brief Unset CRC output reversal
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @retval None * @retval None
*/ */
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/** /**
* @brief Set CRC non-default polynomial * @brief Set CRC non-default polynomial
* @param __HANDLE__: CRC handle * @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None * @retval None
*/ */
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
@ -114,7 +114,7 @@
*/ */
/* Private macros --------------------------------------------------------*/ /* Private macros --------------------------------------------------------*/
/** @addtogroup CRCEx_Private_Macros CRCEx Private Macros /** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{ * @{
*/ */
@ -123,7 +123,6 @@
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD)) ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ #define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
@ -133,14 +132,13 @@
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions CRC Extended Exported Functions /** @addtogroup CRCEx_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions /** @addtogroup CRCEx_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions ****************************/ /* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);

59
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cryp.h
View file

@ -41,7 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(AES)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -145,11 +145,29 @@ typedef enum
#define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */ #define HAL_CRYP_READ_ERROR ((uint32_t)0x00000002) /*!< Read error */
#define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */ #define HAL_CRYP_DMA_ERROR ((uint32_t)0x00000004) /*!< DMA error */
#define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */ #define HAL_CRYP_BUSY_ERROR ((uint32_t)0x00000008) /*!< Busy flag error */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL CRYP common Callback ID enumeration definition
*/
typedef enum
{
HAL_CRYP_INPUTCPLT_CB_ID = 0x01U, /*!< CRYP input DMA transfer completion callback ID */
HAL_CRYP_OUTPUTCPLT_CB_ID = 0x02U, /*!< CRYP output DMA transfer completion callback ID */
HAL_CRYP_COMPCPLT_CB_ID = 0x03U, /*!< CRYP computation completion callback ID */
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP error callback ID */
HAL_CRYP_MSPINIT_CB_ID = 0x05U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x06U, /*!< CRYP MspDeInit callback ID */
}HAL_CRYP_CallbackIDTypeDef;
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/** /**
* @brief CRYP handle Structure definition * @brief CRYP handle Structure definition
*/ */
typedef struct typedef struct __CRYP_HandleTypeDef
{ {
AES_TypeDef *Instance; /*!< Register base address */ AES_TypeDef *Instance; /*!< Register base address */
@ -180,8 +198,30 @@ typedef struct
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP input DMA transfer completion callback */
void (* OutCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP output DMA transfer completion callback */
void (* CompCpltCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP computation completion callback */
void (* ErrorCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP error callback */
void (* MspInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */
void (* MspDeInitCallback)( struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
}CRYP_HandleTypeDef; }CRYP_HandleTypeDef;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL CRYP Callback pointer definition
*/
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a CRYP common callback functions */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -348,7 +388,15 @@ typedef struct
* @param __HANDLE__: specifies the CRYP handle. * @param __HANDLE__: specifies the CRYP handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/** /**
* @brief Enable the CRYP AES peripheral. * @brief Enable the CRYP AES peripheral.
@ -645,6 +693,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uin
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/** /**
* @} * @}
@ -685,7 +738,7 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
* @} * @}
*/ */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* AES */
#ifdef __cplusplus #ifdef __cplusplus
} }

5
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_cryp_ex.h
View file

@ -41,8 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(AES)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -135,7 +134,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp);
* @} * @}
*/ */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* AES */
#ifdef __cplusplus #ifdef __cplusplus
} }

70
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dac.h
View file

@ -75,7 +75,7 @@ typedef enum
/** /**
* @brief DAC handle Structure definition * @brief DAC handle Structure definition
*/ */
typedef struct typedef struct __DAC_HandleTypeDef
{ {
DAC_TypeDef *Instance; /*!< Register base address */ DAC_TypeDef *Instance; /*!< Register base address */
@ -89,6 +89,20 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */ __IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}DAC_HandleTypeDef; }DAC_HandleTypeDef;
/** /**
@ -144,6 +158,31 @@ typedef struct
}DAC_ChannelConfTypeDef; }DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DAC Callback ID enumeration definition
*/
typedef enum
{
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
}HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -157,11 +196,15 @@ typedef struct
/** @defgroup DAC_Error_Code DAC Error Code /** @defgroup DAC_Error_Code DAC Error Code
* @{ * @{
*/ */
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
#define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */ #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -340,7 +383,15 @@ typedef struct
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__: specifies the DAC handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel. /** @brief Enable the DAC channel.
* @param __HANDLE__: specifies the DAC handle. * @param __HANDLE__: specifies the DAC handle.
@ -502,6 +553,13 @@ void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

156
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dcmi.h
View file

@ -41,12 +41,10 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
#if defined (DCMI)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
@ -61,6 +59,7 @@
/** @defgroup DCMI_Exported_Types DCMI Exported Types /** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{ * @{
*/ */
/** /**
* @brief DCMI Embedded Synchronisation CODE Init structure definition * @brief DCMI Embedded Synchronisation CODE Init structure definition
*/ */
@ -91,40 +90,39 @@ typedef struct
typedef struct typedef struct
{ {
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode. */ This parameter can be a value of @ref DCMI_Synchronization_Mode */
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity. */ This parameter can be a value of @ref DCMI_PIXCK_Polarity */
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity. */ This parameter can be a value of @ref DCMI_VSYNC_Polarity */
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity. */ This parameter can be a value of @ref DCMI_HSYNC_Polarity */
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate. */ This parameter can be a value of @ref DCMI_Capture_Rate */
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode. */ This parameter can be a value of @ref DCMI_Extended_Data_Mode */
DCMI_CodesInitTypeDef SynchroCode; /*!< Specifies the frame start delimiter codes. */ DCMI_CodesInitTypeDef SynchroCode; /*!< Specifies the frame start delimiter codes. */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_JPEG_Mode. */ This parameter can be a value of @ref DCMI_MODE_JPEG */
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface. uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMI_Byte_Select_Mode. */ This parameter can be a value of @ref DCMI_Byte_Select_Mode */
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd. uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Byte_Select_Start. */ This parameter can be a value of @ref DCMI_Byte_Select_Start */
uint32_t LineSelectMode; /*!< Specifies the data line to be captured by the interface. uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
This parameter can be a value of @ref DCMI_Line_Select_Mode. */ This parameter can be a value of @ref DCMI_Line_Select_Mode */
uint32_t LineSelectStart; /*!< Specifies if the data line to be captured by the interface is even or odd.
This parameter can be a value of @ref DCMI_Line_Select_Start. */
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
}DCMI_InitTypeDef; }DCMI_InitTypeDef;
@ -145,7 +143,7 @@ typedef enum
/** /**
* @brief DCMI handle Structure definition * @brief DCMI handle Structure definition
*/ */
typedef struct typedef struct __DCMI_HandleTypeDef
{ {
DCMI_TypeDef *Instance; /*!< DCMI Register base address */ DCMI_TypeDef *Instance; /*!< DCMI Register base address */
@ -174,7 +172,32 @@ typedef struct
uint32_t HalfCopyLength; /*!< Intermediate copies length uint32_t HalfCopyLength; /*!< Intermediate copies length
(case picture size > maximum DMA transfer length) */ (case picture size > maximum DMA transfer length) */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}DCMI_HandleTypeDef; }DCMI_HandleTypeDef;
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
typedef enum
{
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
}HAL_DCMI_CallbackIDTypeDef;
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -187,11 +210,14 @@ typedef struct
/** @defgroup DCMI_Error_Code DCMI Error Code /** @defgroup DCMI_Error_Code DCMI Error Code
* @{ * @{
*/ */
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001) /*!< Overrun error */ #define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */ #define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ #define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error */ #define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -199,7 +225,7 @@ typedef struct
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{ * @{
*/ */
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously #define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
into the destination memory through the DMA */ into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of #define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */ frame and then transfers a single frame through the DMA */
@ -210,7 +236,7 @@ typedef struct
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{ * @{
*/ */
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop) #define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */ is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with #define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */ synchronization codes embedded in the data flow */
@ -222,7 +248,7 @@ typedef struct
/** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity /** @defgroup DCMI_PIXCK_Polarity DCMI Pixel Clock Polarity
* @{ * @{
*/ */
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
/** /**
@ -232,7 +258,7 @@ typedef struct
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{ * @{
*/ */
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */ #define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
/** /**
@ -242,7 +268,7 @@ typedef struct
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{ * @{
*/ */
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */ #define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
/** /**
@ -252,7 +278,7 @@ typedef struct
/** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode /** @defgroup DCMI_JPEG_Mode DCMI JPEG Mode
* @{ * @{
*/ */
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< JPEG mode disabled */ #define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< JPEG mode disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< JPEG mode enabled */ #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< JPEG mode enabled */
/** /**
@ -262,7 +288,7 @@ typedef struct
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{ * @{
*/ */
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */ #define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
@ -273,7 +299,7 @@ typedef struct
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{ * @{
*/ */
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
@ -285,7 +311,7 @@ typedef struct
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode /** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
* @{ * @{
*/ */
#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */ #define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */ #define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ #define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ #define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
@ -297,7 +323,7 @@ typedef struct
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start /** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
* @{ * @{
*/ */
#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */ #define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */ #define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
/** /**
@ -307,7 +333,7 @@ typedef struct
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode /** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
* @{ * @{
*/ */
#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */ #define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ #define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
/** /**
@ -317,7 +343,7 @@ typedef struct
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start /** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
* @{ * @{
*/ */
#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */ #define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */ #define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/** /**
@ -377,21 +403,29 @@ typedef struct
*/ */
/** @brief Reset DCMI handle state /** @brief Reset DCMI handle state
* @param __HANDLE__: specifies the DCMI handle. * @param __HANDLE__ specifies the DCMI handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/** /**
* @brief Enable the DCMI. * @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @retval None * @retval None
*/ */
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
/** /**
* @brief Disable the DCMI. * @brief Disable the DCMI.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @retval None * @retval None
*/ */
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
@ -399,8 +433,8 @@ typedef struct
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
* @brief Get the DCMI pending flag. * @brief Get the DCMI pending flag.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__ Get the specified flag.
* This parameter can be one of the following values (no combination allowed) * This parameter can be one of the following values (no combination allowed)
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
@ -423,8 +457,8 @@ typedef struct
/** /**
* @brief Clear the DCMI pending flag. * @brief Clear the DCMI pending flag.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag
* @arg DCMI_FLAG_OVRRI: Overrun flag * @arg DCMI_FLAG_OVRRI: Overrun flag
@ -437,8 +471,8 @@ typedef struct
/** /**
* @brief Enable the specified DCMI interrupts. * @brief Enable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_FRAME: Frame capture complete interrupt
* @arg DCMI_IT_OVR: Overrun interrupt * @arg DCMI_IT_OVR: Overrun interrupt
@ -451,8 +485,8 @@ typedef struct
/** /**
* @brief Disable the specified DCMI interrupts. * @brief Disable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt * @arg DCMI_IT_FRAME: Frame capture complete interrupt
* @arg DCMI_IT_OVR: Overrun interrupt * @arg DCMI_IT_OVR: Overrun interrupt
@ -464,11 +498,11 @@ typedef struct
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/** /**
* @brief Check whether or not the specified DCMI interrupt has occurred and that the interruption is enabled at the same time. * @brief Check whether the specified DCMI interrupt has occurred or not.
* @note A bit in MIS register is set if the corresponding enable bit in * @note A bit in MIS register is set if the corresponding enable bit in
* DCMI_IER is set and the corresponding bit in DCMI_RIS is set. * DCMI_IER is set and the corresponding bit in DCMI_RIS is set.
* @param __HANDLE__: DCMI handle * @param __HANDLE__ DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt flag and source to check. * @param __INTERRUPT__ specifies the DCMI interrupt flag and source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVR: Overrun interrupt mask * @arg DCMI_IT_OVR: Overrun interrupt mask
@ -497,6 +531,12 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -555,8 +595,8 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/** @defgroup DCMI_Registers_Indices DCMI Registers Indices /** @defgroup DCMI_Registers_Indices DCMI Registers Indices
* @{ * @{
*/ */
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ #define DCMI_MIS_INDEX ((uint32_t)0x1000U) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ #define DCMI_SR_INDEX ((uint32_t)0x2000U) /*!< DCMI SR register index */
/** /**
* @} * @}
*/ */
@ -564,7 +604,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{ * @{
*/ */
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */ #define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
/** /**
* @} * @}
*/ */
@ -572,7 +612,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/** @defgroup DCMI_Window_Height DCMI Window Height /** @defgroup DCMI_Window_Height DCMI Window Height
* @{ * @{
*/ */
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */ #define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
/** /**
* @} * @}
*/ */
@ -630,9 +670,6 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ #define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN)) ((POLARITY) == DCMI_OELS_EVEN))
#define IS_DCMI_INTERRUPTS(INTERRUPTS) ((INTERRUPTS) <= DCMI_IER_INT_IE)
/** /**
* @} * @}
*/ */
@ -645,8 +682,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
* @} * @}
*/ */
#endif /* STM32L496xx || STM32L4A6xx || */ #endif /* DCMI */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_def.h
View file

@ -71,10 +71,12 @@ typedef enum
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \ do{ \
@ -82,8 +84,6 @@ typedef enum
(__DMA_HANDLE__).Parent = (__HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0) } while(0)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle. * @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:

203
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dfsdm.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DFSDM_H #ifndef STM32L4xx_HAL_DFSDM_H
#define __STM32L4xx_HAL_DFSDM_H #define STM32L4xx_HAL_DFSDM_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -140,13 +140,37 @@ typedef struct
/** /**
* @brief DFSDM channel handle structure definition * @brief DFSDM channel handle structure definition
*/ */
typedef struct typedef struct __DFSDM_Channel_HandleTypeDef
{ {
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
#endif
} DFSDM_Channel_HandleTypeDef; } DFSDM_Channel_HandleTypeDef;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief DFSDM channel callback ID enumeration definition
*/
typedef enum
{
HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */
HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */
HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */
} HAL_DFSDM_Channel_CallbackIDTypeDef;
/**
* @brief DFSDM channel callback pointer definition
*/
typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
#endif
/** /**
* @brief HAL DFSDM Filter states definition * @brief HAL DFSDM Filter states definition
*/ */
@ -212,7 +236,7 @@ typedef struct
/** /**
* @brief DFSDM filter handle structure definition * @brief DFSDM filter handle structure definition
*/ */
typedef struct typedef struct __DFSDM_Filter_HandleTypeDef
{ {
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
@ -227,6 +251,17 @@ typedef struct
uint32_t InjConvRemaining; /*!< Injected conversions remaining */ uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */ uint32_t ErrorCode; /*!< DFSDM filter error code */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */
void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */
void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */
void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */
void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */
void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */
void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */
#endif
} DFSDM_Filter_HandleTypeDef; } DFSDM_Filter_HandleTypeDef;
/** /**
@ -248,6 +283,28 @@ typedef struct
This parameter can be a values combination of @ref DFSDM_BreakSignals */ This parameter can be a values combination of @ref DFSDM_BreakSignals */
} DFSDM_Filter_AwdParamTypeDef; } DFSDM_Filter_AwdParamTypeDef;
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/**
* @brief DFSDM filter callback ID enumeration definition
*/
typedef enum
{
HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */
HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */
HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */
HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */
HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */
HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */
HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */
} HAL_DFSDM_Filter_CallbackIDTypeDef;
/**
* @brief DFSDM filter callback pointer definition
*/
typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
#endif
/** /**
* @} * @}
*/ */
@ -261,7 +318,7 @@ typedef struct
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{ * @{
*/ */
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
/** /**
* @} * @}
@ -270,7 +327,7 @@ typedef struct
/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
* @{ * @{
*/ */
#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
@ -284,7 +341,7 @@ typedef struct
/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
* @{ * @{
*/ */
#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */
#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
/** /**
@ -294,7 +351,7 @@ typedef struct
/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
* @{ * @{
*/ */
#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */
#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
/** /**
* @} * @}
@ -303,7 +360,7 @@ typedef struct
/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
* @{ * @{
*/ */
#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */
#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
@ -314,7 +371,7 @@ typedef struct
/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
* @{ * @{
*/ */
#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
@ -325,7 +382,7 @@ typedef struct
/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
* @{ * @{
*/ */
#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
@ -336,9 +393,9 @@ typedef struct
/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
* @{ * @{
*/ */
#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */
#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */
/** /**
* @} * @}
*/ */
@ -347,7 +404,7 @@ typedef struct
* @{ * @{
*/ */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
@ -355,7 +412,7 @@ typedef struct
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */
#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
@ -371,7 +428,7 @@ typedef struct
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */
#else #else
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
@ -400,7 +457,7 @@ typedef struct
/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
* @{ * @{
*/ */
#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
@ -413,7 +470,7 @@ typedef struct
/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
* @{ * @{
*/ */
#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
/** /**
* @} * @}
@ -422,10 +479,13 @@ typedef struct
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{ * @{
*/ */
#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
#endif
/** /**
* @} * @}
*/ */
@ -433,11 +493,11 @@ typedef struct
/** @defgroup DFSDM_BreakSignals DFSDM break signals /** @defgroup DFSDM_BreakSignals DFSDM break signals
* @{ * @{
*/ */
#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */
#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */
#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */
#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */
#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */
/** /**
* @} * @}
*/ */
@ -454,19 +514,19 @@ typedef struct
- the channel number 5 is 0x00050000 - the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) #define DFSDM_CHANNEL_0 0x00000001U
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_1 0x00010002U
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) #define DFSDM_CHANNEL_2 0x00020004U
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) #define DFSDM_CHANNEL_3 0x00030008U
#else #else
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) #define DFSDM_CHANNEL_0 0x00000001U
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) #define DFSDM_CHANNEL_1 0x00010002U
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) #define DFSDM_CHANNEL_2 0x00020004U
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) #define DFSDM_CHANNEL_3 0x00030008U
#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) #define DFSDM_CHANNEL_4 0x00040010U
#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) #define DFSDM_CHANNEL_5 0x00050020U
#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) #define DFSDM_CHANNEL_6 0x00060040U
#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) #define DFSDM_CHANNEL_7 0x00070080U
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
/** /**
* @} * @}
@ -475,8 +535,8 @@ typedef struct
/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
* @{ * @{
*/ */
#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */
#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */
/** /**
* @} * @}
*/ */
@ -484,8 +544,8 @@ typedef struct
/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
* @{ * @{
*/ */
#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */
#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */
/** /**
* @} * @}
*/ */
@ -504,13 +564,29 @@ typedef struct
* @param __HANDLE__ DFSDM channel handle. * @param __HANDLE__ DFSDM channel handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
#endif
/** @brief Reset DFSDM filter handle state. /** @brief Reset DFSDM filter handle state.
* @param __HANDLE__ DFSDM filter handle. * @param __HANDLE__ DFSDM filter handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
#endif
/** /**
* @} * @}
@ -535,6 +611,15 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Channel callbacks register/unregister functions ****************************/
HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
pDFSDM_Channel_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);
#endif
/** /**
* @} * @}
*/ */
@ -582,6 +667,18 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
/* Filter callbacks register/unregister functions ****************************/
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
pDFSDM_Filter_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
pDFSDM_Filter_AwdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
#endif
/** /**
* @} * @}
*/ */
@ -665,7 +762,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
*/ */
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \ defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
@ -695,10 +792,10 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U))
#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU)
#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU)
#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
@ -747,8 +844,8 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC5_ORDER)) ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U))
#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U))
#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
@ -758,7 +855,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \
((CHANNEL) == DFSDM_CHANNEL_2) || \ ((CHANNEL) == DFSDM_CHANNEL_2) || \
((CHANNEL) == DFSDM_CHANNEL_3)) ((CHANNEL) == DFSDM_CHANNEL_3))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU)) #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
#else #else
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
((CHANNEL) == DFSDM_CHANNEL_1) || \ ((CHANNEL) == DFSDM_CHANNEL_1) || \
@ -768,7 +865,7 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
((CHANNEL) == DFSDM_CHANNEL_5) || \ ((CHANNEL) == DFSDM_CHANNEL_5) || \
((CHANNEL) == DFSDM_CHANNEL_6) || \ ((CHANNEL) == DFSDM_CHANNEL_6) || \
((CHANNEL) == DFSDM_CHANNEL_7)) ((CHANNEL) == DFSDM_CHANNEL_7))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON)) ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
@ -793,6 +890,6 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
} }
#endif #endif
#endif /* __STM32L4xx_HAL_DFSDM_H */ #endif /* STM32L4xx_HAL_DFSDM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dfsdm_ex.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DFSDM_EX_H #ifndef STM32L4xx_HAL_DFSDM_EX_H
#define __STM32L4xx_HAL_DFSDM_EX_H #define STM32L4xx_HAL_DFSDM_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -104,6 +104,6 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD
} }
#endif #endif
#endif /* __STM32L4xx_HAL_DFSDM_EX_H */ #endif /* STM32L4xx_HAL_DFSDM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

70
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma.h
View file

@ -95,10 +95,10 @@ typedef struct
*/ */
typedef enum typedef enum
{ {
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef; }HAL_DMA_StateTypeDef;
/** /**
@ -106,8 +106,8 @@ typedef enum
*/ */
typedef enum typedef enum
{ {
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef; }HAL_DMA_LevelCompleteTypeDef;
@ -116,12 +116,11 @@ typedef enum
*/ */
typedef enum typedef enum
{ {
HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef; }HAL_DMA_CallbackIDTypeDef;
/** /**
@ -169,6 +168,7 @@ typedef struct __DMA_HandleTypeDef
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
}DMA_HandleTypeDef; }DMA_HandleTypeDef;
/** /**
* @} * @}
*/ */
@ -182,13 +182,13 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Error_Code DMA Error Code /** @defgroup DMA_Error_Code DMA Error Code
* @{ * @{
*/ */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
/** /**
* @} * @}
@ -199,14 +199,14 @@ typedef struct __DMA_HandleTypeDef
*/ */
#if !defined (DMAMUX1) #if !defined (DMAMUX1)
#define DMA_REQUEST_0 ((uint32_t)0x00000000) #define DMA_REQUEST_0 0U
#define DMA_REQUEST_1 ((uint32_t)0x00000001) #define DMA_REQUEST_1 1U
#define DMA_REQUEST_2 ((uint32_t)0x00000002) #define DMA_REQUEST_2 2U
#define DMA_REQUEST_3 ((uint32_t)0x00000003) #define DMA_REQUEST_3 3U
#define DMA_REQUEST_4 ((uint32_t)0x00000004) #define DMA_REQUEST_4 4U
#define DMA_REQUEST_5 ((uint32_t)0x00000005) #define DMA_REQUEST_5 5U
#define DMA_REQUEST_6 ((uint32_t)0x00000006) #define DMA_REQUEST_6 6U
#define DMA_REQUEST_7 ((uint32_t)0x00000007) #define DMA_REQUEST_7 7U
#endif #endif
@ -339,9 +339,9 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{ * @{
*/ */
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/** /**
* @} * @}
*/ */
@ -349,8 +349,8 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{ * @{
*/ */
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/** /**
* @} * @}
*/ */
@ -358,8 +358,8 @@ typedef struct __DMA_HandleTypeDef
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{ * @{
*/ */
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/** /**
* @} * @}
*/ */
@ -701,7 +701,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY)) ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE)) ((STATE) == DMA_PINC_DISABLE))

209
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma2d.h
View file

@ -34,16 +34,14 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DMA2D_H #ifndef STM32L4xx_HAL_DMA2D_H
#define __STM32L4xx_HAL_DMA2D_H #define STM32L4xx_HAL_DMA2D_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L496xx) || defined(STM32L4A6xx) || \ #if defined (DMA2D)
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -60,7 +58,7 @@
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{ * @{
*/ */
#define MAX_DMA2D_LAYER 2U #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
/** /**
* @brief DMA2D color Structure definition * @brief DMA2D color Structure definition
@ -104,7 +102,6 @@ typedef struct
uint32_t OutputOffset; /*!< Specifies the Offset value. uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
@ -112,14 +109,16 @@ typedef struct
for the output pixel format converter. for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */ This parameter can be one value of @ref DMA2D_RB_Swap. */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two).
This parameter can be one value of @ref DMA2D_Bytes_Swap. */ This parameter can be one value of @ref DMA2D_Bytes_Swap. */
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output.
This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
} DMA2D_InitTypeDef; } DMA2D_InitTypeDef;
@ -146,12 +145,13 @@ typedef struct
- InputAlpha[16:23] is the red value RED[0:7] - InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7] - InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */ - InputAlpha[0:7] is the blue value BLUE[0:7]. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap. */ This parameter can be one value of @ref DMA2D_RB_Swap. */
} DMA2D_LayerCfgTypeDef; } DMA2D_LayerCfgTypeDef;
/** /**
@ -180,6 +180,17 @@ typedef struct __DMA2D_HandleTypeDef
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */
void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */
void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */
void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */ HAL_LockTypeDef Lock; /*!< DMA2D lock. */
@ -188,6 +199,13 @@ typedef struct __DMA2D_HandleTypeDef
__IO uint32_t ErrorCode; /*!< DMA2D error code. */ __IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef; } DMA2D_HandleTypeDef;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D Callback pointer definition
*/
typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -200,11 +218,15 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Error_Code DMA2D Error Code /** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{ * @{
*/ */
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */ #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */
#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */ #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -212,14 +234,14 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Mode DMA2D Mode /** @defgroup DMA2D_Mode DMA2D Mode
* @{ * @{
*/ */
#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */ #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
#define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
#define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
/** /**
* @} * @}
*/ */
@ -227,7 +249,7 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{ * @{
*/ */
#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
@ -239,17 +261,17 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{ * @{
*/ */
#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */ #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */
#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */ #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */
#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */ #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */
#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */ #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */
#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */ #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */
#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */ #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */
#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */ #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */
#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */ #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */
#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */ #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */
#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */ #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */
#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */ #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */
/** /**
* @} * @}
*/ */
@ -257,9 +279,9 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{ * @{
*/ */
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */ #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */ with original alpha channel value */
/** /**
* @} * @}
@ -268,8 +290,8 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
* @{ * @{
*/ */
#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */ #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */
#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */ #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */
/** /**
* @} * @}
*/ */
@ -277,38 +299,42 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{ * @{
*/ */
#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */ #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */
#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */ #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */
/** /**
* @} * @}
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
* @{ * @{
*/ */
#define DMA2D_LOM_PIXELS ((uint32_t)0x00000000U) /*!< Line offsets expressed in pixels */ #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */
#define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */
/** /**
* @} * @}
*/ */
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
* @{ * @{
*/ */
#define DMA2D_BYTES_REGULAR ((uint32_t)0x00000000U) /*!< Bytes in regular order in output FIFO */ #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */
#define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */
/** /**
* @} * @}
*/ */
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{ * @{
*/ */
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */ #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */ #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */
/** /**
* @} * @}
*/ */
@ -347,6 +373,21 @@ typedef struct __DMA2D_HandleTypeDef
* @} * @}
*/ */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D common Callback ID enumeration definition
*/
typedef enum
{
HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */
HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */
HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */
HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */
HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */
HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */
}HAL_DMA2D_CallbackIDTypeDef;
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/** /**
* @} * @}
@ -357,14 +398,23 @@ typedef struct __DMA2D_HandleTypeDef
*/ */
/** @brief Reset DMA2D handle state /** @brief Reset DMA2D handle state
* @param __HANDLE__: specifies the DMA2D handle. * @param __HANDLE__ specifies the DMA2D handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/** /**
* @brief Enable the DMA2D. * @brief Enable the DMA2D.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @retval None. * @retval None.
*/ */
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
@ -373,8 +423,8 @@ typedef struct __DMA2D_HandleTypeDef
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
* @brief Get the DMA2D pending flags. * @brief Get the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @param __FLAG__: flag to check. * @param __FLAG__ flag to check.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
@ -388,8 +438,8 @@ typedef struct __DMA2D_HandleTypeDef
/** /**
* @brief Clear the DMA2D pending flags. * @brief Clear the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
@ -403,8 +453,8 @@ typedef struct __DMA2D_HandleTypeDef
/** /**
* @brief Enable the specified DMA2D interrupts. * @brief Enable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
@ -418,8 +468,8 @@ typedef struct __DMA2D_HandleTypeDef
/** /**
* @brief Disable the specified DMA2D interrupts. * @brief Disable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
@ -433,8 +483,8 @@ typedef struct __DMA2D_HandleTypeDef
/** /**
* @brief Check whether the specified DMA2D interrupt source is enabled or not. * @brief Check whether the specified DMA2D interrupt source is enabled or not.
* @param __HANDLE__: DMA2D handle * @param __HANDLE__ DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check. * @param __INTERRUPT__ specifies the DMA2D interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
@ -464,6 +514,11 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/** /**
* @} * @}
@ -546,7 +601,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Color_Value DMA2D Color Value /** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{ * @{
*/ */
#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */
/** /**
* @} * @}
*/ */
@ -554,7 +609,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{ * @{
*/ */
#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */ #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @}
*/
/** @defgroup DMA2D_Layers DMA2D Layers
* @{
*/
#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */
#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */
/** /**
* @} * @}
*/ */
@ -562,7 +626,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Offset DMA2D Offset /** @defgroup DMA2D_Offset DMA2D Offset
* @{ * @{
*/ */
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
/** /**
* @} * @}
*/ */
@ -570,8 +634,8 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Size DMA2D Size /** @defgroup DMA2D_Size DMA2D Size
* @{ * @{
*/ */
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
/** /**
* @} * @}
*/ */
@ -579,7 +643,7 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{ * @{
*/ */
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */ #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */
/** /**
* @} * @}
*/ */
@ -593,30 +657,33 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{ * @{
*/ */
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
#else #else
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4)) ((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA)) ((AlphaMode) == DMA2D_COMBINE_ALPHA))
@ -627,14 +694,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP)) ((RB_Swap) == DMA2D_RB_SWAP))
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
#define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
((LOM) == DMA2D_LOM_BYTES)) ((LOM) == DMA2D_LOM_BYTES))
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
((BYTES_SWAP) == DMA2D_BYTES_SWAP)) ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
#endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
@ -657,13 +726,13 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @} * @}
*/ */
#endif /* STM32L496xx || STM32L4A6xx || */ #endif /* DMA2D */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32L4xx_HAL_DMA2D_H */ #endif /* STM32L4xx_HAL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

62
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dma_ex.h
View file

@ -164,32 +164,32 @@ typedef struct
* @{ * @{
*/ */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ #define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ #define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ #define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ #define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */
/** /**
* @} * @}
@ -198,10 +198,10 @@ typedef struct
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{ * @{
*/ */
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ #define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */
#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ #define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ #define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ #define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/** /**
* @} * @}
@ -265,7 +265,7 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE)) ((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))

97
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_dsi.h
View file

@ -34,18 +34,17 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_DSI_H #ifndef STM32L4xx_HAL_DSI_H
#define __STM32L4xx_HAL_DSI_H #define STM32L4xx_HAL_DSI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(DSI)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
#if defined(DSI)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
@ -316,7 +315,7 @@ typedef enum
/** /**
* @brief DSI Handle Structure definition * @brief DSI Handle Structure definition
*/ */
typedef struct typedef struct __DSI_HandleTypeDef
{ {
DSI_TypeDef *Instance; /*!< Register base address */ DSI_TypeDef *Instance; /*!< Register base address */
DSI_InitTypeDef Init; /*!< DSI required parameters */ DSI_InitTypeDef Init; /*!< DSI required parameters */
@ -324,8 +323,41 @@ typedef struct
__IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */
__IO uint32_t ErrorCode; /*!< DSI Error code */ __IO uint32_t ErrorCode; /*!< DSI Error code */
uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ uint32_t ErrorMsk; /*!< DSI Error monitoring mask */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */
void (* EndOfRefreshCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */
void (* ErrorCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */
void (* MspInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */
void (* MspDeInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}DSI_HandleTypeDef; }DSI_HandleTypeDef;
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DSI Callback ID enumeration definition
*/
typedef enum
{
HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */
HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */
HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */
HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */
HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */
}HAL_DSI_CallbackIDTypeDef;
/**
* @brief HAL DSI Callback pointer definition
*/
typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef * hdsi); /*!< pointer to an DSI callback function */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_DCS_Command DSI DCS Command /** @defgroup DSI_DCS_Command DSI DCS Command
* @{ * @{
@ -827,6 +859,9 @@ typedef struct
#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -891,11 +926,19 @@ typedef struct
* @param __HANDLE__: DSI handle * @param __HANDLE__: DSI handle
* @retval None * @retval None
*/ */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_DSI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
/** /**
* @brief Enables the DSI host. * @brief Enables the DSI host.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_ENABLE(__HANDLE__) do { \ #define __HAL_DSI_ENABLE(__HANDLE__) do { \
@ -908,7 +951,7 @@ typedef struct
/** /**
* @brief Disables the DSI host. * @brief Disables the DSI host.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_DISABLE(__HANDLE__) do { \ #define __HAL_DSI_DISABLE(__HANDLE__) do { \
@ -921,7 +964,7 @@ typedef struct
/** /**
* @brief Enables the DSI wrapper. * @brief Enables the DSI wrapper.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
@ -934,7 +977,7 @@ typedef struct
/** /**
* @brief Disable the DSI wrapper. * @brief Disable the DSI wrapper.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
@ -947,7 +990,7 @@ typedef struct
/** /**
* @brief Enables the DSI PLL. * @brief Enables the DSI PLL.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
@ -960,7 +1003,7 @@ typedef struct
/** /**
* @brief Disables the DSI PLL. * @brief Disables the DSI PLL.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
@ -973,7 +1016,7 @@ typedef struct
/** /**
* @brief Enables the DSI regulator. * @brief Enables the DSI regulator.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
@ -986,7 +1029,7 @@ typedef struct
/** /**
* @brief Disables the DSI regulator. * @brief Disables the DSI regulator.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @retval None. * @retval None.
*/ */
#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
@ -999,8 +1042,8 @@ typedef struct
/** /**
* @brief Get the DSI pending flags. * @brief Get the DSI pending flags.
* @param __HANDLE__: DSI handle. * @param __HANDLE__ DSI handle.
* @param __FLAG__: Get the specified flag. * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
@ -1016,8 +1059,8 @@ typedef struct
/** /**
* @brief Clears the DSI pending flags. * @brief Clears the DSI pending flags.
* @param __HANDLE__: DSI handle. * @param __HANDLE__ DSI handle.
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
@ -1030,8 +1073,8 @@ typedef struct
/** /**
* @brief Enables the specified DSI interrupts. * @brief Enables the specified DSI interrupts.
* @param __HANDLE__: DSI handle. * @param __HANDLE__ DSI handle.
* @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt
@ -1044,8 +1087,8 @@ typedef struct
/** /**
* @brief Disables the specified DSI interrupts. * @brief Disables the specified DSI interrupts.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt
@ -1058,8 +1101,8 @@ typedef struct
/** /**
* @brief Checks whether the specified DSI interrupt source is enabled or not. * @brief Checks whether the specified DSI interrupt source is enabled or not.
* @param __HANDLE__: DSI handle * @param __HANDLE__ DSI handle
* @param __INTERRUPT__: specifies the DSI interrupt source to check. * @param __INTERRUPT__ specifies the DSI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt
@ -1084,6 +1127,12 @@ void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@ -1291,6 +1340,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
} }
#endif #endif
#endif /* __STM32L4xx_HAL_DSI_H */ #endif /* STM32L4xx_HAL_DSI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

107
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_flash.h
View file

@ -161,22 +161,22 @@ typedef struct
/** @defgroup FLASH_Error FLASH Error /** @defgroup FLASH_Error FLASH Error
* @{ * @{
*/ */
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) #define HAL_FLASH_ERROR_NONE 0x00000000U
#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) #define HAL_FLASH_ERROR_PEMPTY FLASH_FLAG_PEMPTY
#endif #endif
/** /**
* @} * @}
@ -535,6 +535,15 @@ typedef struct
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */ #define FLASH_FLAG_PEMPTY FLASH_SR_PEMPTY /*!< FLASH Program empty */
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
FLASH_FLAG_OPTVERR | FLASH_FLAG_PEMPTY)
#else
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
FLASH_FLAG_OPTVERR)
#endif #endif
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
@ -695,8 +704,8 @@ typedef struct
* @arg FLASH_IT_ECCC: ECC Correction Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt
* @retval none * @retval none
*/ */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0) } while(0)
/** /**
@ -709,8 +718,8 @@ typedef struct
* @arg FLASH_IT_ECCC: ECC Correction Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt
* @retval none * @retval none
*/ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0) } while(0)
/** /**
@ -734,7 +743,7 @@ typedef struct
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
* @retval The new state of FLASH_FLAG (SET or RESET). * @retval The new state of FLASH_FLAG (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
@ -758,8 +767,8 @@ typedef struct
* @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
* @retval None * @retval None
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
} while(0) } while(0)
/** /**
* @} * @}
@ -823,20 +832,20 @@ uint32_t HAL_FLASH_GetError(void);
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x800U << 10U) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200U << 10U) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))
#else #else
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ #define FLASH_SIZE ((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x400U << 10U) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))
#endif #endif
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \ defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1U)
#else #else
#define FLASH_BANK_SIZE (FLASH_SIZE) #define FLASH_BANK_SIZE (FLASH_SIZE)
#endif #endif
@ -881,34 +890,34 @@ uint32_t HAL_FLASH_GetError(void);
((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((ADDRESS) <= (FLASH_BASE+0x1FFFFFU)))
#else #else
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= (FLASH_BASE)) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? \
((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? \
((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ ((ADDRESS) <= (FLASH_BASE+0x7FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? \
((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ ((ADDRESS) <= (FLASH_BASE+0x3FFFFU)) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? \
((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) ((ADDRESS) <= (FLASH_BASE+0x1FFFFU)) : ((ADDRESS) <= (FLASH_BASE+0xFFFFFU)))))))
#endif #endif
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS)))
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) #define IS_FLASH_PAGE(PAGE) ((PAGE) < 256U)
#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x400U) ? ((PAGE) < 256U) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 128U) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 64U) : \
((PAGE) < 256))))) ((PAGE) < 256U)))))
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x200U) ? ((PAGE) < 256U) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
((PAGE) < 256)))) ((PAGE) < 256U))))
#else #else
#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ #define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x100U) ? ((PAGE) < 128U) : \
((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) == 0x80U) ? ((PAGE) < 64U) : \
((PAGE) < 128)))) ((PAGE) < 128U))))
#endif #endif
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
@ -927,11 +936,11 @@ uint32_t HAL_FLASH_GetError(void);
((LEVEL) == OB_RDP_LEVEL_2)*/) ((LEVEL) == OB_RDP_LEVEL_2)*/)
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFFU) && ((TYPE) != 0U))
#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFU) && ((TYPE) != 0U))
#else #else
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7FU) && ((TYPE) != 0U) && (((TYPE)&0x0180U) == 0U))
#endif #endif
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \

33
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_flash_ramfunc.h
View file

@ -54,39 +54,6 @@
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions /** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{ * @{

49
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_gfxmmu.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_GFXMMU_H #ifndef STM32L4xx_HAL_GFXMMU_H
#define __STM32L4xx_HAL_GFXMMU_H #define STM32L4xx_HAL_GFXMMU_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -105,12 +105,17 @@ typedef struct
/** /**
* @brief GFXMMU handle structure definition * @brief GFXMMU handle structure definition
*/ */
typedef struct typedef struct __GFXMMU_HandleTypeDef
{ {
GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */ GFXMMU_TypeDef *Instance; /*!< GFXMMU instance */
GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */ GFXMMU_InitTypeDef Init; /*!< GFXMMU init parameters */
HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */ HAL_GFXMMU_StateTypeDef State; /*!< GFXMMU state */
__IO uint32_t ErrorCode; /*!< GFXMMU error code */ __IO uint32_t ErrorCode; /*!< GFXMMU error code */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
void (*ErrorCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
void (*MspInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
#endif
}GFXMMU_HandleTypeDef; }GFXMMU_HandleTypeDef;
/** /**
@ -132,6 +137,23 @@ typedef struct
LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */ LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
}GFXMMU_LutLineTypeDef; }GFXMMU_LutLineTypeDef;
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief GFXMMU callback ID enumeration definition
*/
typedef enum
{
HAL_GFXMMU_ERROR_CB_ID = 0x00U, /*!< GFXMMU error callback ID */
HAL_GFXMMU_MSPINIT_CB_ID = 0x01U, /*!< GFXMMU MSP init callback ID */
HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U /*!< GFXMMU MSP de-init callback ID */
}HAL_GFXMMU_CallbackIDTypeDef;
/**
* @brief GFXMMU callback pointer definition
*/
typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
#endif
/** /**
* @} * @}
*/ */
@ -172,6 +194,9 @@ typedef struct
#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */ #define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */ #define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
#define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */ #define GFXMMU_ERROR_AHB_MASTER GFXMMU_SR_AMEF /*!< AHB master error */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -199,7 +224,15 @@ typedef struct
* @param __HANDLE__ GFXMMU handle. * @param __HANDLE__ GFXMMU handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET) #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
#endif
/** /**
* @} * @}
@ -219,6 +252,14 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu); HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu); void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* GFXMMU callbacks register/unregister functions *****************************/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID);
#endif
/** /**
* @} * @}
*/ */
@ -301,6 +342,6 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
} }
#endif #endif
#endif /* __STM32L4xx_HAL_GFXMMU_H */ #endif /* STM32L4xx_HAL_GFXMMU_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_gpio_ex.h
View file

@ -682,7 +682,7 @@
*/ */
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ #define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ #define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_DSI ((uint8_t)0x0C) /* DSI Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ #define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */

66
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_hash.h
View file

@ -110,11 +110,25 @@ typedef enum
HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */ HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */
}HAL_HASH_SuspendTypeDef; }HAL_HASH_SuspendTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
/**
* @brief HAL HASH common Callback ID enumeration definition
*/
typedef enum
{
HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */
HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */
HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */
HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */
HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */
}HAL_HASH_CallbackIDTypeDef;
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/** /**
* @brief HASH Handle Structure definition * @brief HASH Handle Structure definition
*/ */
typedef struct typedef struct __HASH_HandleTypeDef
{ {
HASH_InitTypeDef Init; /*!< HASH required parameters */ HASH_InitTypeDef Init; /*!< HASH required parameters */
@ -150,8 +164,29 @@ typedef struct
__IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */
__IO uint32_t ErrorCode; /*!< HASH Error code */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */
void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */
void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */
void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */
void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
} HASH_HandleTypeDef; } HASH_HandleTypeDef;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
/**
* @brief HAL HASH Callback pointer definition
*/
typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -234,6 +269,18 @@ typedef struct
*/ */
/** @defgroup HASH_Error_Definition HASH Error Definition
* @{
*/
#define HAL_HASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_HASH_ERROR_IT ((uint32_t)0x00000001U) /*!< IT-based process error */
#define HAL_HASH_ERROR_DMA ((uint32_t)0x00000002U) /*!< DMA-based process error */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
#define HAL_HASH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid Callback error */
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
/** /**
* @} * @}
@ -291,7 +338,17 @@ typedef struct
* @param __HANDLE__: HASH handle. * @param __HANDLE__: HASH handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_HASH_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
#else
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/** @brief Reset HASH handle status. /** @brief Reset HASH handle status.
* @param __HANDLE__: HASH handle. * @param __HANDLE__: HASH handle.
@ -438,6 +495,12 @@ void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/** /**
* @} * @}
@ -531,6 +594,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
/** /**
* @} * @}

121
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_hcd.h
View file

@ -41,13 +41,11 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_usb.h" #include "stm32l4xx_ll_usb.h"
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
@ -85,15 +83,27 @@ typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition /** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{ * @{
*/ */
typedef struct typedef struct __HCD_HandleTypeDef
{ {
HCD_TypeDef *Instance; /*!< Register base address */ HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */ HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ HCD_HCTypeDef hc[16]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */ __IO HCD_StateTypeDef State; /*!< HCD communication state */
__IO uint32_t ErrorCode; /*!< HCD Error code */
void *pData; /*!< Pointer Stack Handler */ void *pData; /*!< Pointer Stack Handler */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */
void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */
void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */
void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */
void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */
void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,
HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */
void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */
void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
} HCD_HandleTypeDef; } HCD_HandleTypeDef;
/** /**
* @} * @}
@ -111,9 +121,9 @@ typedef struct
/** @defgroup HCD_Speed HCD Speed /** @defgroup HCD_Speed HCD Speed
* @{ * @{
*/ */
#define HCD_SPEED_HIGH 0 #define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2 #define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3 #define HCD_SPEED_FULL 3U
/** /**
* @} * @}
*/ */
@ -121,7 +131,20 @@ typedef struct
/** @defgroup HCD_PHY_Module HCD PHY Module /** @defgroup HCD_PHY_Module HCD PHY Module
* @{ * @{
*/ */
#define HCD_PHY_EMBEDDED 1 #define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
/**
* @}
*/
/** @defgroup HCD_Error_Code_definition HCD Error Code definition
* @brief HCD Error Code definition
* @{
*/
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -135,12 +158,12 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations * @brief macros to handle interrupts and specific clock configurations
* @{ * @{
*/ */
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) #define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
@ -156,8 +179,7 @@ typedef struct
* @{ * @{
*/ */
/* Initialization/de-initialization functions ********************************/ /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
@ -170,11 +192,50 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ep_type, uint8_t ep_type,
uint16_t mps); uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition
* @brief HAL USB OTG HCD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */
HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */
HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */
HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */
HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */
HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */
HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */
} HAL_HCD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition
* @brief HAL USB OTG HCD Callback pointer definition
* @{
*/
typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */
typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,
uint8_t epnum,
HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */
/**
* @}
*/
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -197,6 +258,8 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
uint8_t chnum, uint8_t chnum,
HCD_URBStateTypeDef urb_state); HCD_URBStateTypeDef urb_state);
@ -242,6 +305,24 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
* @} * @}
*/ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -250,9 +331,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
* @} * @}
*/ */
#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

94
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_I2C_H #ifndef STM32L4xx_HAL_I2C_H
#define __STM32L4xx_HAL_I2C_H #define STM32L4xx_HAL_I2C_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -186,6 +186,11 @@ typedef enum
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/** /**
* @} * @}
*/ */
@ -226,7 +231,54 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef; } I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -248,6 +300,13 @@ typedef struct __I2C_HandleTypeDef
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/** /**
* @} * @}
*/ */
@ -396,7 +455,15 @@ typedef struct __I2C_HandleTypeDef
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif
/** @brief Enable the specified I2C interrupt. /** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
@ -528,6 +595,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -568,6 +644,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/** /**
* @} * @}
*/ */
@ -659,7 +740,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME)) ((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
@ -703,6 +789,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif #endif
#endif /* __STM32L4xx_HAL_I2C_H */ #endif /* STM32L4xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_i2c_ex.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_I2C_EX_H #ifndef STM32L4xx_HAL_I2C_EX_H
#define __STM32L4xx_HAL_I2C_EX_H #define STM32L4xx_HAL_I2C_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -181,6 +181,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
} }
#endif #endif
#endif /* __STM32L4xx_HAL_I2C_EX_H */ #endif /* STM32L4xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

106
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_irda.h
View file

@ -154,20 +154,6 @@ typedef enum
Value is allowed for gState only */ Value is allowed for gState only */
} HAL_IRDA_StateTypeDef; } HAL_IRDA_StateTypeDef;
/**
* @brief HAL IRDA Error Code structure definition
*/
typedef enum
{
HAL_IRDA_ERROR_NONE = 0x00U, /*!< No error */
HAL_IRDA_ERROR_PE = 0x01U, /*!< Parity error */
HAL_IRDA_ERROR_NE = 0x02U, /*!< Noise error */
HAL_IRDA_ERROR_FE = 0x04U, /*!< frame error */
HAL_IRDA_ERROR_ORE = 0x08U, /*!< Overrun error */
HAL_IRDA_ERROR_DMA = 0x10U, /*!< DMA transfer error */
HAL_IRDA_ERROR_BUSY = 0x20U /*!< Busy Error */
}HAL_IRDA_ErrorTypeDef;
/** /**
* @brief IRDA clock sources definition * @brief IRDA clock sources definition
*/ */
@ -184,7 +170,7 @@ typedef enum
/** /**
* @brief IRDA handle Structure definition * @brief IRDA handle Structure definition
*/ */
typedef struct typedef struct __IRDA_HandleTypeDef
{ {
USART_TypeDef *Instance; /*!< USART registers base address */ USART_TypeDef *Instance; /*!< USART registers base address */
@ -219,8 +205,58 @@ typedef struct
uint32_t ErrorCode; /*!< IRDA Error code */ uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
} IRDA_HandleTypeDef; } IRDA_HandleTypeDef;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief HAL IRDA Callback ID enumeration definition
*/
typedef enum
{
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
} HAL_IRDA_CallbackIDTypeDef;
/**
* @brief HAL IRDA Callback pointer definition
*/
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/** /**
* @brief IRDA Configuration enumeration values definition * @brief IRDA Configuration enumeration values definition
*/ */
@ -243,6 +279,23 @@ typedef enum
* @{ * @{
*/ */
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Word_Length IRDA Word Length /** @defgroup IRDA_Word_Length IRDA Word Length
* @{ * @{
*/ */
@ -425,7 +478,7 @@ typedef enum
*/ */
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ #define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
@ -455,10 +508,19 @@ typedef enum
* @param __HANDLE__ IRDA handle. * @param __HANDLE__ IRDA handle.
* @retval None * @retval None
*/ */
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0) } while(0)
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register. /** @brief Flush the IRDA DR register.
* @param __HANDLE__ specifies the IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle.
@ -657,7 +719,7 @@ typedef enum
*/ */
/* Private macros --------------------------------------------------------*/ /* Private macros --------------------------------------------------------*/
/** @defgroup IRDA_Private_Macros IRDA Private Macros /** @addtogroup IRDA_Private_Macros
* @{ * @{
*/ */
@ -738,7 +800,7 @@ typedef enum
* @param __MODE__ IRDA communication mode. * @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/ */
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00)) #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** /**
* @brief Ensure that IRDA power mode is valid. * @brief Ensure that IRDA power mode is valid.
@ -778,7 +840,7 @@ typedef enum
/** /**
* @brief Ensure that IRDA associated UART/USART mode is valid. * @brief Ensure that IRDA associated UART/USART mode is valid.
* @param __MODE__: IRDA associated UART/USART mode. * @param __MODE__ IRDA associated UART/USART mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/ */
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ #define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
@ -838,6 +900,12 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

8
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_irda_ex.h
View file

@ -48,7 +48,7 @@
* @{ * @{
*/ */
/** @addtogroup IRDAEx /** @defgroup IRDAEx IRDAEx
* @{ * @{
*/ */
@ -68,9 +68,9 @@
* @param __CLOCKSOURCE__ output variable. * @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__. * @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/ */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \
defined (STM32L496xx) || defined (STM32L4A6xx) || \ || defined (STM32L496xx) || defined (STM32L4A6xx) \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
if((__HANDLE__)->Instance == USART1) \ if((__HANDLE__)->Instance == USART1) \

50
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_lptim.h
View file

@ -152,7 +152,7 @@ typedef enum __HAL_LPTIM_StateTypeDef
/** /**
* @brief LPTIM handle Structure definition * @brief LPTIM handle Structure definition
*/ */
typedef struct typedef struct __LPTIM_HandleTypeDef
{ {
LPTIM_TypeDef *Instance; /*!< Register base address */ LPTIM_TypeDef *Instance; /*!< Register base address */
@ -164,8 +164,42 @@ typedef struct
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}LPTIM_HandleTypeDef; }LPTIM_HandleTypeDef;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LPTIM Callback ID enumeration definition
*/
typedef enum
{
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
} HAL_LPTIM_CallbackIDTypeDef;
/**
* @brief HAL TIM Callback pointer definition
*/
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -352,7 +386,15 @@ typedef struct
* @param __HANDLE__: LPTIM handle * @param __HANDLE__: LPTIM handle
* @retval None * @retval None
*/ */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/** /**
* @brief Enable the LPTIM peripheral. * @brief Enable the LPTIM peripheral.
@ -557,6 +599,12 @@ void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/* Peripheral State functions ************************************************/ /* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);

112
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc.h
View file

@ -34,14 +34,14 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_LTDC_H #ifndef STM32L4xx_HAL_LTDC_H
#define __STM32L4xx_HAL_LTDC_H #define STM32L4xx_HAL_LTDC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (LTDC)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -181,7 +181,7 @@ typedef enum
/** /**
* @brief LTDC handle Structure definition * @brief LTDC handle Structure definition
*/ */
typedef struct typedef struct __LTDC_HandleTypeDef
{ {
LTDC_TypeDef *Instance; /*!< LTDC Register base address */ LTDC_TypeDef *Instance; /*!< LTDC Register base address */
@ -195,7 +195,41 @@ typedef struct
__IO uint32_t ErrorCode; /*!< LTDC Error code */ __IO uint32_t ErrorCode; /*!< LTDC Error code */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
void (* LineEventCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
void (* ErrorCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
void (* MspInitCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
void (* MspDeInitCallback) (struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
} LTDC_HandleTypeDef; } LTDC_HandleTypeDef;
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LTDC Callback ID enumeration definition
*/
typedef enum
{
HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
}HAL_LTDC_CallbackIDTypeDef;
/**
* @brief HAL LTDC Callback pointer definition
*/
typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef * hltdc); /*!< pointer to an LTDC callback function */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -208,10 +242,13 @@ typedef struct
/** @defgroup LTDC_Error_Code LTDC Error Code /** @defgroup LTDC_Error_Code LTDC Error Code
* @{ * @{
*/ */
#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */ #define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */ #define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */ #define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */ #define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -219,8 +256,8 @@ typedef struct
/** @defgroup LTDC_Layer LTDC Layer /** @defgroup LTDC_Layer LTDC Layer
* @{ * @{
*/ */
#define LTDC_LAYER_1 ((uint32_t)0x00000000U) /*!< LTDC Layer 1 */ #define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
#define LTDC_LAYER_2 ((uint32_t)0x00000001U) /*!< LTDC Layer 2 */ #define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
/** /**
* @} * @}
*/ */
@ -228,7 +265,7 @@ typedef struct
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY /** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{ * @{
*/ */
#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */ #define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ #define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/** /**
* @} * @}
@ -237,7 +274,7 @@ typedef struct
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY /** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{ * @{
*/ */
#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */ #define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ #define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/** /**
* @} * @}
@ -246,7 +283,7 @@ typedef struct
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY /** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{ * @{
*/ */
#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */ #define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ #define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/** /**
* @} * @}
@ -255,7 +292,7 @@ typedef struct
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY /** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{ * @{
*/ */
#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */ #define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ #define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/** /**
* @} * @}
@ -273,7 +310,7 @@ typedef struct
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR /** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{ * @{
*/ */
#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */ #define LTDC_COLOR 0x000000FFU /*!< Color mask */
/** /**
* @} * @}
*/ */
@ -281,8 +318,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 /** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{ * @{
*/ */
#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */ #define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ #define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/** /**
* @} * @}
*/ */
@ -290,8 +327,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 /** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{ * @{
*/ */
#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */ #define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ #define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/** /**
* @} * @}
*/ */
@ -299,14 +336,14 @@ typedef struct
/** @defgroup LTDC_Pixelformat LTDC Pixel format /** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{ * @{
*/ */
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */ #define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/** /**
* @} * @}
*/ */
@ -375,7 +412,15 @@ typedef struct
* @param __HANDLE__ LTDC handle * @param __HANDLE__ LTDC handle
* @retval None * @retval None
*/ */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/** /**
* @brief Enable the LTDC. * @brief Enable the LTDC.
@ -510,6 +555,13 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -582,7 +634,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/** @defgroup LTDC_Private_Macros LTDC Private Macros /** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{ * @{
*/ */
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) #define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) #define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) #define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
@ -638,12 +690,12 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
* @} * @}
*/ */
#endif /* STM32L4R7xx || STM32L4R9xx || STM32L4R7xx || STM32L4S9xx */ #endif /* LTDC */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32L4xx_HAL_LTDC_H */ #endif /* STM32L4xx_HAL_LTDC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

10
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ltdc_ex.h
View file

@ -34,14 +34,14 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_LTDC_EX_H #ifndef STM32L4xx_HAL_LTDC_EX_H
#define __STM32L4xx_HAL_LTDC_EX_H #define STM32L4xx_HAL_LTDC_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined (STM32L4R9xx) || defined (STM32L4S9xx) #if defined (LTDC) && defined (DSI)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -90,12 +90,12 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
* @} * @}
*/ */
#endif /* STM32L4R9xx || STM32L4S9xx */ #endif /* LTDC && DSI */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32L4xx_HAL_LTDC_EX_H */ #endif /* STM32L4xx_HAL_LTDC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

216
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nand.h
View file

@ -41,9 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ #if defined(FMC_BANK3)
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_fmc.h" #include "stm32l4xx_ll_fmc.h"
@ -56,69 +54,6 @@
* @{ * @{
*/ */
/** @addtogroup NAND_Private_Constants
* @{
*/
#define NAND_DEVICE FMC_BANK3
#define NAND_WRITE_TIMEOUT ((uint32_t)1000)
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define NAND_BUSY ((uint32_t)0x00000000)
#define NAND_ERROR ((uint32_t)0x00000001)
#define NAND_READY ((uint32_t)0x00000040)
/**
* @}
*/
/** @addtogroup NAND_Private_Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__: NAND memory address.
* @param __HANDLE__: NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__: NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/ /* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types /** @defgroup NAND_Exported_Types NAND Exported Types
@ -130,10 +65,10 @@
*/ */
typedef enum typedef enum
{ {
HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
}HAL_NAND_StateTypeDef; }HAL_NAND_StateTypeDef;
/** /**
@ -142,7 +77,6 @@ typedef enum
typedef struct typedef struct
{ {
/*<! NAND memory electronic signature maker and device IDs */ /*<! NAND memory electronic signature maker and device IDs */
uint8_t Maker_Id; uint8_t Maker_Id;
uint8_t Device_Id; uint8_t Device_Id;
@ -159,10 +93,9 @@ typedef struct
{ {
uint16_t Page; /*!< NAND memory Page address */ uint16_t Page; /*!< NAND memory Page address */
uint16_t Zone; /*!< NAND memory Zone address */ uint16_t Plane; /*!< NAND memory Zone address */
uint16_t Block; /*!< NAND memory Block address */ uint16_t Block; /*!< NAND memory Block address */
}NAND_AddressTypeDef; }NAND_AddressTypeDef;
/** /**
@ -170,16 +103,27 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size number of pages */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of blocks */ uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */ uint32_t PlaneNbr; /*!< NAND memory number of planes */
}NAND_InfoTypeDef;
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/** /**
* @brief NAND handle Structure definition * @brief NAND handle Structure definition
@ -194,9 +138,9 @@ typedef struct
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */ NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
}NAND_HandleTypeDef;
} NAND_HandleTypeDef;
/** /**
* @} * @}
*/ */
@ -207,8 +151,8 @@ typedef struct
* @{ * @{
*/ */
/** @brief Reset NAND handle state. /** @brief Reset NAND handle state
* @param __HANDLE__: specifies the NAND handle. * @param __HANDLE__ specifies the NAND handle.
* @retval None * @retval None
*/ */
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
@ -229,6 +173,11 @@ typedef struct
/* Initialization/de-initialization functions ********************************/ /* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
@ -243,14 +192,21 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
*/ */
/* IO operation functions ****************************************************/ /* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
/** /**
@ -273,10 +229,86 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{ * @{
*/ */
/* NAND State functions *******************************************************/ /* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE FMC_BANK3
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NAND_Private_Macros NAND Private Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__ NAND memory address.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @brief NAND memory Columns cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/** /**
* @} * @}
@ -294,9 +326,7 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
* @} * @}
*/ */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* FMC_BANK3 */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

173
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_nor.h
View file

@ -41,9 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ #if defined(FMC_BANK1)
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_fmc.h" #include "stm32l4xx_ll_fmc.h"
@ -57,64 +55,6 @@
* @{ * @{
*/ */
/** @addtogroup NOR_Private_Constants
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x10)
#define CFI2_ADDRESS ((uint16_t)0x11)
#define CFI3_ADDRESS ((uint16_t)0x12)
#define CFI4_ADDRESS ((uint16_t)0x13)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0)
#define NOR_MEMORY_16B ((uint8_t)0x1)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 FMC_BANK1_1
#define NOR_MEMORY_ADRESS2 FMC_BANK1_2
#define NOR_MEMORY_ADRESS3 FMC_BANK1_3
#define NOR_MEMORY_ADRESS4 FMC_BANK1_4
/**
* @}
*/
/** @addtogroup NOR_Private_Macros
* @{
*/
/**
* @brief NOR memory address shifting.
* @param __NOR_ADDRESS: NOR base address
* @param __NOR_MEMORY_WIDTH_: NOR memory width
* @param __ADDRESS__: NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
* @brief NOR memory write data to specified address.
* @param __ADDRESS__: NOR memory address
* @param __DATA__: Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/ /* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types /** @defgroup NOR_Exported_Types NOR Exported Types
* @{ * @{
@ -125,11 +65,11 @@
*/ */
typedef enum typedef enum
{ {
HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
}HAL_NOR_StateTypeDef; }HAL_NOR_StateTypeDef;
/** /**
@ -137,7 +77,7 @@ typedef enum
*/ */
typedef enum typedef enum
{ {
HAL_NOR_STATUS_SUCCESS = 0, HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT HAL_NOR_STATUS_TIMEOUT
@ -165,15 +105,17 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
uint16_t CFI_1; uint16_t CFI_1;
uint16_t CFI_2; uint16_t CFI_2;
uint16_t CFI_3; uint16_t CFI_3;
uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface uint16_t CFI_4;
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory. */
}NOR_CFITypeDef; }NOR_CFITypeDef;
/** /**
@ -190,9 +132,7 @@ typedef struct
HAL_LockTypeDef Lock; /*!< NOR locking object */ HAL_LockTypeDef Lock; /*!< NOR locking object */
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
}NOR_HandleTypeDef; }NOR_HandleTypeDef;
/** /**
* @} * @}
*/ */
@ -202,13 +142,11 @@ typedef struct
/** @defgroup NOR_Exported_Macros NOR Exported Macros /** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{ * @{
*/ */
/** @brief Reset NOR handle state
/** @brief Reset NOR handle state. * @param __HANDLE__ specifies the NOR handle.
* @param __HANDLE__: NOR handle
* @retval None * @retval None
*/ */
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
/** /**
* @} * @}
*/ */
@ -228,7 +166,6 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
/** /**
* @} * @}
*/ */
@ -249,30 +186,96 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
/** /**
* @} * @}
*/ */
/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
* @{ * @{
*/ */
/* NOR Control functions *****************************************************/ /* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
/** /**
* @} * @}
*/ */
/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
* @{ * @{
*/ */
/* NOR State functions ********************************************************/ /* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NOR_Private_Macros NOR Private Macros
* @{
*/
/**
* @brief NOR memory address shifting.
* @param __NOR_ADDRESS NOR base address
* @param __NOR_MEMORY_WIDTH_ NOR memory width
* @param __ADDRESS__ NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
* @brief NOR memory write data to specified address.
* @param __ADDRESS__ NOR memory address
* @param __DATA__ Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
__DSB(); \
} while(0)
/** /**
* @} * @}
@ -286,13 +289,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @} * @}
*/ */
/** #endif /* FMC_BANK1 */
* @}
*/
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

41
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_opamp.h
View file

@ -135,7 +135,7 @@ typedef enum
/** /**
* @brief OPAMP Handle Structure definition * @brief OPAMP Handle Structure definition
*/ */
typedef struct typedef struct __OPAMP_HandleTypeDef
{ {
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */ OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */ OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
@ -143,6 +143,11 @@ typedef struct
HAL_LockTypeDef Lock; /*!< Locking object */ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */ __IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) (struct __OPAMP_HandleTypeDef *hopamp);
void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
} OPAMP_HandleTypeDef; } OPAMP_HandleTypeDef;
/** /**
@ -155,6 +160,24 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
* @} * @}
*/ */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL OPAMP Callback ID enumeration definition
*/
typedef enum
{
HAL_OPAMP_MSP_INIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */
HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */
HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */
}HAL_OPAMP_CallbackIDTypeDef;
/**
* @brief HAL OPAMP Callback pointer definition
*/
typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
@ -282,7 +305,17 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
* @param __HANDLE__: OPAMP handle. * @param __HANDLE__: OPAMP handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_OPAMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET) #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/** /**
* @} * @}
@ -395,6 +428,12 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/* OPAMP callback registering/unregistering */
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID, pOPAMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);

119
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_ospi.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_OSPI_H #ifndef STM32L4xx_HAL_OSPI_H
#define __STM32L4xx_HAL_OSPI_H #define STM32L4xx_HAL_OSPI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -102,7 +102,7 @@ typedef struct
/** /**
* @brief HAL OSPI Handle Structure definition * @brief HAL OSPI Handle Structure definition
*/ */
typedef struct typedef struct __OSPI_HandleTypeDef
{ {
OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ OCTOSPI_TypeDef *Instance; /* OSPI registers base address */
OSPI_InitTypeDef Init; /* OSPI initialization parameters */ OSPI_InitTypeDef Init; /* OSPI initialization parameters */
@ -113,6 +113,21 @@ typedef struct
__IO uint32_t State; /* Internal state of the OSPI HAL driver */ __IO uint32_t State; /* Internal state of the OSPI HAL driver */
__IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */
uint32_t Timeout; /* Timeout used for the OSPI external device access */ uint32_t Timeout; /* Timeout used for the OSPI external device access */
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
#endif
}OSPI_HandleTypeDef; }OSPI_HandleTypeDef;
/** /**
@ -245,6 +260,32 @@ typedef struct
This parameter can be a value of @ref OSPIM_IOPort */ This parameter can be a value of @ref OSPIM_IOPort */
}OSPIM_CfgTypeDef; }OSPIM_CfgTypeDef;
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
/**
* @brief HAL OSPI Callback ID enumeration definition
*/
typedef enum
{
HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */
HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */
HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */
HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */
HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */
HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */
HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */
HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */
HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */
HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */
HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
}HAL_OSPI_CallbackIDTypeDef;
/**
* @brief HAL OSPI Callback pointer definition
*/
typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
#endif
/** /**
* @} * @}
*/ */
@ -283,6 +324,9 @@ typedef struct
#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -603,18 +647,6 @@ typedef struct
#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */
#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */
#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */
#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3)) /*!< Port 3 - IO[3:0] */
#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3)) /*!< Port 3 - IO[7:4] */
#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4)) /*!< Port 4 - IO[3:0] */
#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4)) /*!< Port 4 - IO[7:4] */
#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5)) /*!< Port 5 - IO[3:0] */
#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5)) /*!< Port 5 - IO[7:4] */
#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6)) /*!< Port 6 - IO[3:0] */
#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6)) /*!< Port 6 - IO[7:4] */
#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7)) /*!< Port 7 - IO[3:0] */
#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7)) /*!< Port 7 - IO[7:4] */
#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8)) /*!< Port 8 - IO[3:0] */
#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8)) /*!< Port 8 - IO[7:4] */
/** /**
* @} * @}
*/ */
@ -630,7 +662,15 @@ typedef struct
* @param __HANDLE__: OSPI handle. * @param __HANDLE__: OSPI handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
#endif
/** @brief Enable the OSPI peripheral. /** @brief Enable the OSPI peripheral.
* @param __HANDLE__: specifies the OSPI Handle. * @param __HANDLE__: specifies the OSPI Handle.
@ -697,7 +737,7 @@ typedef struct
* @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
* @retval None * @retval None
*/ */
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified OSPI's flag status. /** @brief Clears the specified OSPI's flag status.
* @param __HANDLE__: specifies the OSPI Handle. * @param __HANDLE__: specifies the OSPI Handle.
@ -779,6 +819,11 @@ void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
/* OSPI memory-mapped mode functions */ /* OSPI memory-mapped mode functions */
void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
#if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1)
/* OSPI callback registering/unregistering */
HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
#endif
/** /**
* @} * @}
*/ */
@ -818,7 +863,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
/** /**
@cond 0 @cond 0
*/ */
#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32)) #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
@ -827,9 +872,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32)) #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U))
#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8)) #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U))
#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
@ -843,7 +888,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \
((SIZE) == HAL_OSPI_WRAP_128_BYTES)) ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256)) #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
@ -906,12 +951,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
((MODE) == HAL_OSPI_DATA_4_LINES) || \ ((MODE) == HAL_OSPI_DATA_4_LINES) || \
((MODE) == HAL_OSPI_DATA_8_LINES)) ((MODE) == HAL_OSPI_DATA_8_LINES))
#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1) #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U)
#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31) #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
((MODE) == HAL_OSPI_DQS_ENABLE)) ((MODE) == HAL_OSPI_DQS_ENABLE))
@ -919,9 +964,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255) #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U)
#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255) #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U)
#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
@ -938,35 +983,23 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF) #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31) #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 8)) #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U))
#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_2_HIGH))
((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
/** /**
@endcond @endcond
*/ */
@ -987,6 +1020,6 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
} }
#endif #endif
#endif /* __STM32L4xx_HAL_OSPI_H */ #endif /* STM32L4xx_HAL_OSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

723
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd.h
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File diff suppressed because it is too large Load diff

37
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_pcd_ex.h
View file

@ -2,7 +2,7 @@
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_pcd_ex.h * @file stm32l4xx_hal_pcd_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of PCD HAL module. * @brief Header file of PCD HAL Extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -41,15 +41,11 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
@ -58,23 +54,6 @@
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
}PCD_BCD_MsgTypeDef;
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
@ -85,10 +64,10 @@ typedef enum
* @{ * @{
*/ */
#if defined(USB_OTG_FS) #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* USB_OTG_FS */ #endif /* USB_OTG_FS || USB_OTG_HS */
#if defined (USB) #if defined (USB)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
@ -120,11 +99,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
* @} * @}
*/ */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ #endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* STM32L452xx || STM32L462xx || */
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

187
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_qspi.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_QSPI_H #ifndef STM32L4xx_HAL_QSPI_H
#define __STM32L4xx_HAL_QSPI_H #define STM32L4xx_HAL_QSPI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -94,21 +94,21 @@ typedef struct
*/ */
typedef enum typedef enum
{ {
HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */ HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */ HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */ HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */ HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */ HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */ HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */ HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */ HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */ HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef; }HAL_QSPI_StateTypeDef;
/** /**
* @brief QSPI Handle Structure definition * @brief QSPI Handle Structure definition
*/ */
typedef struct typedef struct __QSPI_HandleTypeDef
{ {
QUADSPI_TypeDef *Instance; /* QSPI registers base address */ QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */ QSPI_InitTypeDef Init; /* QSPI communication parameters */
@ -123,6 +123,21 @@ typedef struct
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */ __IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */ uint32_t Timeout; /* Timeout for the QSPI memory access */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
#endif
}QSPI_HandleTypeDef; }QSPI_HandleTypeDef;
/** /**
@ -155,8 +170,9 @@ typedef struct
until end of memory)*/ until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */ This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
system clock in DDR mode. Not available on STM32L4x6 devices but in future devices. output by one half of system clock in DDR mode.
Not available on all devices.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */ This parameter can be a value of @ref QSPI_SIOOMode */
@ -192,6 +208,32 @@ typedef struct
This parameter can be a value of @ref QSPI_TimeOutActivation */ This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef; }QSPI_MemoryMappedTypeDef;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/**
* @brief HAL QSPI Callback ID enumeration definition
*/
typedef enum
{
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
}HAL_QSPI_CallbackIDTypeDef;
/**
* @brief HAL QSPI Callback pointer definition
*/
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#endif
/** /**
* @} * @}
*/ */
@ -204,11 +246,14 @@ typedef struct
/** @defgroup QSPI_ErrorCode QSPI Error Code /** @defgroup QSPI_ErrorCode QSPI Error Code
* @{ * @{
*/ */
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */ #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */ #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */ #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */ #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -216,7 +261,7 @@ typedef struct
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{ * @{
*/ */
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/ #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/** /**
* @} * @}
@ -225,7 +270,7 @@ typedef struct
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{ * @{
*/ */
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/ #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@ -240,7 +285,7 @@ typedef struct
/** @defgroup QSPI_ClockMode QSPI Clock Mode /** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{ * @{
*/ */
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/ #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/** /**
* @} * @}
@ -250,7 +295,7 @@ typedef struct
/** @defgroup QSPI_Flash_Select QSPI Flash Select /** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{ * @{
*/ */
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/ #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/** /**
* @} * @}
@ -260,16 +305,16 @@ typedef struct
* @{ * @{
*/ */
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/ #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/** /**
* @} * @}
*/ */
#endif
#endif
/** @defgroup QSPI_AddressSize QSPI Address Size /** @defgroup QSPI_AddressSize QSPI Address Size
* @{ * @{
*/ */
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/ #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@ -280,7 +325,7 @@ typedef struct
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{ * @{
*/ */
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/ #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@ -291,7 +336,7 @@ typedef struct
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{ * @{
*/ */
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/ #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@ -302,7 +347,7 @@ typedef struct
/** @defgroup QSPI_AddressMode QSPI Address Mode /** @defgroup QSPI_AddressMode QSPI Address Mode
* @{ * @{
*/ */
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/ #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@ -313,7 +358,7 @@ typedef struct
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{ * @{
*/ */
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/ #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@ -324,7 +369,7 @@ typedef struct
/** @defgroup QSPI_DataMode QSPI Data Mode /** @defgroup QSPI_DataMode QSPI Data Mode
* @{ * @{
*/ */
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ #define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@ -335,7 +380,7 @@ typedef struct
/** @defgroup QSPI_DdrMode QSPI DDR Mode /** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{ * @{
*/ */
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/ #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/** /**
* @} * @}
@ -344,9 +389,9 @@ typedef struct
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{ * @{
*/ */
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/ #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#if defined(QUADSPI_CCR_DHHC) #if defined(QUADSPI_CCR_DHHC)
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/
#endif #endif
/** /**
* @} * @}
@ -355,7 +400,7 @@ typedef struct
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{ * @{
*/ */
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/ #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/** /**
* @} * @}
@ -364,7 +409,7 @@ typedef struct
/** @defgroup QSPI_MatchMode QSPI Match Mode /** @defgroup QSPI_MatchMode QSPI Match Mode
* @{ * @{
*/ */
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/ #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/** /**
* @} * @}
@ -373,7 +418,7 @@ typedef struct
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{ * @{
*/ */
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/ #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/** /**
* @} * @}
@ -382,7 +427,7 @@ typedef struct
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{ * @{
*/ */
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/ #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/** /**
* @} * @}
@ -417,7 +462,7 @@ typedef struct
* @brief QSPI Timeout definition * @brief QSPI Timeout definition
* @{ * @{
*/ */
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/** /**
* @} * @}
*/ */
@ -434,7 +479,15 @@ typedef struct
* @param __HANDLE__ : QSPI handle. * @param __HANDLE__ : QSPI handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
#endif
/** @brief Enable the QSPI peripheral. /** @brief Enable the QSPI peripheral.
* @param __HANDLE__ : specifies the QSPI Handle. * @param __HANDLE__ : specifies the QSPI Handle.
@ -501,7 +554,7 @@ typedef struct
* @arg QSPI_FLAG_TE: QSPI Transfer error flag * @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None * @retval None
*/ */
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET) #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status. /** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__ : specifies the QSPI Handle. * @param __HANDLE__ : specifies the QSPI Handle.
@ -522,12 +575,22 @@ typedef struct
/** @addtogroup QSPI_Exported_Functions /** @addtogroup QSPI_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup QSPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/ /* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
/* QSPI IRQ handler method */ /* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
@ -567,6 +630,18 @@ void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */ /* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* QSPI callback registering/unregistering */
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID);
#endif
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/ /* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
@ -575,6 +650,13 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
#if defined(QUADSPI_CR_DFM)
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
#endif
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -584,14 +666,14 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
/** @defgroup QSPI_Private_Macros QSPI Private Macros /** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{ * @{
*/ */
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16)) #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
@ -606,14 +688,14 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
((CLKMODE) == QSPI_CLOCK_MODE_3)) ((CLKMODE) == QSPI_CLOCK_MODE_3))
#if defined(QUADSPI_CR_DFM) #if defined(QUADSPI_CR_DFM)
#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \ #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH) == QSPI_FLASH_ID_2)) ((FLASH_ID) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE)) ((MODE) == QSPI_DUALFLASH_DISABLE))
#endif
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) #endif
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
@ -625,7 +707,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \ ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
@ -653,16 +735,17 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
#if defined(QUADSPI_CCR_DHHC) #if defined(QUADSPI_CCR_DHHC)
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#else #else
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
#endif
#endif
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR)) ((MODE) == QSPI_MATCH_MODE_OR))
@ -673,7 +756,7 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/** /**
* @} * @}
*/ */
@ -693,6 +776,6 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
} }
#endif #endif
#endif /* __STM32L4xx_HAL_QSPI_H */ #endif /* STM32L4xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

306
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rcc.h
View file

@ -82,7 +82,8 @@ typedef struct
This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
uint32_t PLLR; /*!< PLLR: Division for the main system clock. uint32_t PLLR; /*!< PLLR: Division for the main system clock.
User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. User have to set the PLLR parameter correctly to not exceed max frequency 120MHZ
on STM32L4Rx/STM32L4Sx devices else 80MHz on the other devices.
This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
}RCC_PLLInitTypeDef; }RCC_PLLInitTypeDef;
@ -161,7 +162,7 @@ typedef struct
/** @defgroup RCC_Timeout_Value Timeout Values /** @defgroup RCC_Timeout_Value Timeout Values
* @{ * @{
*/ */
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
/** /**
* @} * @}
@ -170,14 +171,14 @@ typedef struct
/** @defgroup RCC_Oscillator_Type Oscillator Type /** @defgroup RCC_Oscillator_Type Oscillator Type
* @{ * @{
*/ */
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */ #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
/** /**
* @} * @}
@ -186,9 +187,9 @@ typedef struct
/** @defgroup RCC_HSE_Config HSE Config /** @defgroup RCC_HSE_Config HSE Config
* @{ * @{
*/ */
#define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
/** /**
* @} * @}
*/ */
@ -196,9 +197,9 @@ typedef struct
/** @defgroup RCC_LSE_Config LSE Config /** @defgroup RCC_LSE_Config LSE Config
* @{ * @{
*/ */
#define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */ #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
/** /**
* @} * @}
*/ */
@ -206,14 +207,14 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config /** @defgroup RCC_HSI_Config HSI Config
* @{ * @{
*/ */
#define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */ #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
#else #else
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */ #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/** /**
@ -223,7 +224,7 @@ typedef struct
/** @defgroup RCC_LSI_Config LSI Config /** @defgroup RCC_LSI_Config LSI Config
* @{ * @{
*/ */
#define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */ #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
/** /**
* @} * @}
@ -232,10 +233,10 @@ typedef struct
/** @defgroup RCC_MSI_Config MSI Config /** @defgroup RCC_MSI_Config MSI Config
* @{ * @{
*/ */
#define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */ #define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */
#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */ #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */
/** /**
* @} * @}
*/ */
@ -244,7 +245,7 @@ typedef struct
/** @defgroup RCC_HSI48_Config HSI48 Config /** @defgroup RCC_HSI48_Config HSI48 Config
* @{ * @{
*/ */
#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
/** /**
* @} * @}
@ -253,7 +254,7 @@ typedef struct
/** @defgroup RCC_HSI48_Config HSI48 Config /** @defgroup RCC_HSI48_Config HSI48 Config
* @{ * @{
*/ */
#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
/** /**
* @} * @}
*/ */
@ -262,9 +263,9 @@ typedef struct
/** @defgroup RCC_PLL_Config PLL Config /** @defgroup RCC_PLL_Config PLL Config
* @{ * @{
*/ */
#define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */ #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
#define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */ #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
#define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */ #define RCC_PLL_ON 0x00000002U /*!< PLL activation */
/** /**
* @} * @}
*/ */
@ -273,39 +274,39 @@ typedef struct
* @{ * @{
*/ */
#if defined(RCC_PLLP_DIV_2_31_SUPPORT) #if defined(RCC_PLLP_DIV_2_31_SUPPORT)
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */ #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */ #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */ #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */ #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */ #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */ #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */ #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */ #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */ #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */ #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */ #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */ #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */ #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */ #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */ #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */ #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */ #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */ #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */ #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */ #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */ #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */ #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */ #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */ #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */ #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */ #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */ #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */ #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
#else #else
#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
/** /**
* @} * @}
@ -314,10 +315,10 @@ typedef struct
/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
* @{ * @{
*/ */
#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */ #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */ #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */ #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */ #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
/** /**
* @} * @}
*/ */
@ -325,10 +326,10 @@ typedef struct
/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
* @{ * @{
*/ */
#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */ #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */ #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */ #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */ #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
/** /**
* @} * @}
*/ */
@ -336,7 +337,7 @@ typedef struct
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{ * @{
*/ */
#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
@ -410,10 +411,10 @@ typedef struct
/** @defgroup RCC_System_Clock_Type System Clock Type /** @defgroup RCC_System_Clock_Type System Clock Type
* @{ * @{
*/ */
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
/** /**
* @} * @}
*/ */
@ -471,7 +472,7 @@ typedef struct
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{ * @{
*/ */
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */ #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
@ -482,7 +483,7 @@ typedef struct
/** @defgroup RCC_MCO_Index MCO Index /** @defgroup RCC_MCO_Index MCO Index
* @{ * @{
*/ */
#define RCC_MCO1 ((uint32_t)0x00000000U) #define RCC_MCO1 0x00000000U
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
/** /**
* @} * @}
@ -491,7 +492,7 @@ typedef struct
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{ * @{
*/ */
#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
@ -551,34 +552,33 @@ typedef struct
* @{ * @{
*/ */
/* Flags in the CR register */ /* Flags in the CR register */
#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */ #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */
#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)) /*!< PLLSAI1 Ready flag */ #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */
#if defined(RCC_PLLSAI2_SUPPORT) #if defined(RCC_PLLSAI2_SUPPORT)
#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)) /*!< PLLSAI2 Ready flag */ #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */
#endif /* RCC_PLLSAI2_SUPPORT */ #endif /* RCC_PLLSAI2_SUPPORT */
/* Flags in the BDCR register */ /* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
/* Flags in the CSR register */ /* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< LSI Ready flag */ #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ #define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */
#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)) /*!< Firewall reset flag */ #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
/* Flags in the CRRCR register */ /* Flags in the CRRCR register */
#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
/** /**
* @} * @}
@ -587,7 +587,7 @@ typedef struct
/** @defgroup RCC_LSEDrive_Config LSE Drive Config /** @defgroup RCC_LSEDrive_Config LSE Drive Config
* @{ * @{
*/ */
#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */ #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
@ -598,7 +598,7 @@ typedef struct
/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
* @{ * @{
*/ */
#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ #define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
/** /**
* @} * @}
@ -3701,13 +3701,13 @@ typedef struct
/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage * @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC. * and temperature that influence the frequency of the internal HSI RC.
* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
* (default is RCC_HSICALIBRATION_DEFAULT). * (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
* @retval None * @retval None
*/ */
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
/** /**
* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
@ -3759,13 +3759,13 @@ typedef struct
* and temperature that influence the frequency of the internal MSI RC. * and temperature that influence the frequency of the internal MSI RC.
* Refer to the Application Note AN3300 for more details on how to * Refer to the Application Note AN3300 for more details on how to
* calibrate the MSI. * calibrate the MSI.
* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value
* (default is RCC_MSICALIBRATION_DEFAULT). * (default is RCC_MSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 255. * This parameter must be a number between 0 and 255.
* @retval None * @retval None
*/ */
#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos)
/** /**
* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
@ -3777,7 +3777,7 @@ typedef struct
* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
* (MSIRDY=1). * (MSIRDY=1).
* @note The MSI clock range after reset can be modified on the fly. * @note The MSI clock range after reset can be modified on the fly.
* @param __MSIRANGEVALUE__: specifies the MSI clock range. * @param __MSIRANGEVALUE__ specifies the MSI clock range.
* This parameter must be one of the following values: * This parameter must be one of the following values:
* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
@ -3802,7 +3802,7 @@ typedef struct
/** /**
* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
* @param __MSIRANGEVALUE__: specifies the MSI clock range. * @param __MSIRANGEVALUE__ specifies the MSI clock range.
* This parameter must be one of the following values: * This parameter must be one of the following values:
* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
@ -3831,8 +3831,8 @@ typedef struct
*/ */
#define __HAL_RCC_GET_MSI_RANGE() \ #define __HAL_RCC_GET_MSI_RANGE() \
((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \
(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U)
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on * @note After enabling the LSI, the application software should wait on
@ -3862,7 +3862,7 @@ typedef struct
* @note This function reset the CSSON bit, so if the clock security system(CSS) * @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this * was previously enabled you have to enable it again after calling this
* function. * function.
* @param __STATE__: specifies the new state of the HSE. * @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles. * 6 HSE oscillator clock cycles.
@ -3900,7 +3900,7 @@ typedef struct
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock * software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC. * is stable and can be used to clock the RTC.
* @param __STATE__: specifies the new state of the LSE. * @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles. * 6 LSE oscillator clock cycles.
@ -3950,9 +3950,9 @@ typedef struct
* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR). * a Power On Reset (POR).
* *
* @param __RTC_CLKSOURCE__: specifies the RTC clock source. * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
@ -3971,12 +3971,12 @@ typedef struct
/** @brief Macro to get the RTC clock source. /** @brief Macro to get the RTC clock source.
* @retval The returned value can be one of the following: * @retval The returned value can be one of the following:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
*/ */
#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
/** @brief Macros to enable or disable the main PLL. /** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on * @note After enabling the main PLL, the application software should wait on
@ -3992,7 +3992,7 @@ typedef struct
/** @brief Macro to configure the PLL clock source. /** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled. * @note This function must be used only when the main PLL is disabled.
* @param __PLLSOURCE__: specifies the PLL entry clock source. * @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
@ -4007,7 +4007,7 @@ typedef struct
/** @brief Macro to configure the PLL source division factor M. /** @brief Macro to configure the PLL source division factor M.
* @note This function must be used only when the main PLL is disabled. * @note This function must be used only when the main PLL is disabled.
* @param __PLLM__: specifies the division factor for PLL VCO input clock * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
* This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input * @note You have to set the PLLM parameter correctly to ensure that the VCO input
@ -4023,7 +4023,7 @@ typedef struct
* @brief Macro to configure the main PLL clock source, multiplication and division factors. * @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled. * @note This function must be used only when the main PLL is disabled.
* *
* @param __PLLSOURCE__: specifies the PLL entry clock source. * @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
@ -4031,29 +4031,29 @@ typedef struct
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
* *
* @param __PLLM__: specifies the division factor for PLL VCO input clock. * @param __PLLM__ specifies the division factor for PLL VCO input clock.
* This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices.
* This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input * @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
* of 16 MHz to limit PLL jitter. * of 16 MHz to limit PLL jitter.
* *
* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock. * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
* This parameter must be a number between 8 and 86. * This parameter must be a number between 8 and 86.
* @note You have to set the PLLN parameter correctly to ensure that the VCO * @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 64 and 344 MHz. * output frequency is between 64 and 344 MHz.
* *
* @param __PLLP__: specifies the division factor for SAI clock. * @param __PLLP__ specifies the division factor for SAI clock.
* This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
* else (2 to 31). * else (2 to 31).
* *
* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
* This parameter must be in the range (2, 4, 6 or 8). * This parameter must be in the range (2, 4, 6 or 8).
* @note If the USB OTG FS is used in your application, you have to set the * @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However, * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
* correctly. * correctly.
* @param __PLLR__: specifies the division factor for the main system clock. * @param __PLLR__ specifies the division factor for the main system clock.
* @note You have to set the PLLR parameter correctly to not exceed 80MHZ. * @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
* This parameter must be in the range (2, 4, 6 or 8). * This parameter must be in the range (2, 4, 6 or 8).
* @retval None * @retval None
@ -4062,14 +4062,14 @@ typedef struct
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
(uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \
(uint32_t)((__PLLP__) << 27U)) ((uint32_t)(__PLLP__) << 27U))
#else #else
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \
(uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \
(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ #endif /* RCC_PLLP_DIV_2_31_SUPPORT */
@ -4081,14 +4081,14 @@ typedef struct
* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
*/ */
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
/** /**
* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
* be stopped if used as System Clock. * be stopped if used as System Clock.
* @param __PLLCLOCKOUT__: specifies the PLL clock to be output. * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
* This parameter can be one or a combination of the following values: * This parameter can be one or a combination of the following values:
* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
* high-quality audio performance on SAI interface in case. * high-quality audio performance on SAI interface in case.
@ -4103,7 +4103,7 @@ typedef struct
/** /**
* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked. * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
* high-quality audio performance on SAI interface in case. * high-quality audio performance on SAI interface in case.
@ -4116,7 +4116,7 @@ typedef struct
/** /**
* @brief Macro to configure the system clock source. * @brief Macro to configure the system clock source.
* @param __SYSCLKSOURCE__: specifies the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
@ -4135,7 +4135,7 @@ typedef struct
* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
*/ */
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
/** /**
* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
@ -4143,7 +4143,7 @@ typedef struct
* this domain after reset, you have to enable write access using * this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset). * (to be done once after reset).
* @param __LSEDRIVE__: specifies the new state of the LSE drive capability. * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
@ -4152,11 +4152,11 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
/** /**
* @brief Macro to configure the wake up from stop clock. * @brief Macro to configure the wake up from stop clock.
* @param __STOPWUCLK__: specifies the clock source used after wake up from stop. * @param __STOPWUCLK__ specifies the clock source used after wake up from stop.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
@ -4199,9 +4199,8 @@ typedef struct
* @{ * @{
*/ */
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable /** @brief Enable RCC interrupt(s).
* the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt
@ -4222,9 +4221,8 @@ typedef struct
*/ */
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable /** @brief Disable RCC interrupt(s).
* the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled.
* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt
@ -4245,9 +4243,8 @@ typedef struct
*/ */
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] /** @brief Clear the RCC's interrupt pending bits.
* bits to clear the selected interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt
@ -4267,10 +4264,10 @@ typedef struct
@endif @endif
* @retval None * @retval None
*/ */
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__))
/** @brief Check whether the RCC interrupt has occurred or not. /** @brief Check whether the RCC interrupt has occurred or not.
* @param __INTERRUPT__: specifies the RCC interrupt source to check. * @param __INTERRUPT__ specifies the RCC interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt
@ -4290,17 +4287,17 @@ typedef struct
@endif @endif
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/ */
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Set RMVF bit to clear the reset flags. /** @brief Set RMVF bit to clear the reset flags.
* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
* @retval None * @retval None
*/ */
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
/** @brief Check whether the selected RCC flag is set or not. /** @brief Check whether the selected RCC flag is set or not.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
@ -4321,7 +4318,6 @@ typedef struct
* @arg @ref RCC_FLAG_OBLRST OBLRST reset * @arg @ref RCC_FLAG_OBLRST OBLRST reset
* @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_PINRST Pin reset
* @arg @ref RCC_FLAG_FWRST FIREWALL reset * @arg @ref RCC_FLAG_FWRST FIREWALL reset
* @arg @ref RCC_FLAG_RMVF Remove reset Flag
* @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_SFTRST Software reset
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
@ -4333,14 +4329,12 @@ typedef struct
((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
? 1U : 0U)
#else #else
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U)
? 1U : 0U)
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
/** /**
@ -4356,14 +4350,14 @@ typedef struct
* @{ * @{
*/ */
/* Defines used for Flags */ /* Defines used for Flags */
#define CR_REG_INDEX ((uint32_t)1U) #define CR_REG_INDEX 1U
#define BDCR_REG_INDEX ((uint32_t)2U) #define BDCR_REG_INDEX 2U
#define CSR_REG_INDEX ((uint32_t)3U) #define CSR_REG_INDEX 3U
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define CRRCR_REG_INDEX ((uint32_t)4U) #define CRRCR_REG_INDEX 4U
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
#define RCC_FLAG_MASK ((uint32_t)0x1FU) #define RCC_FLAG_MASK 0x1FU
/** /**
* @} * @}
*/ */
@ -4398,13 +4392,13 @@ typedef struct
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U)
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
@ -4491,7 +4485,7 @@ typedef struct
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
((__PCLK__) == RCC_HCLK_DIV16)) ((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
@ -4548,7 +4542,7 @@ typedef struct
*/ */
/* Initialization and de-initialization functions ******************************/ /* Initialization and de-initialization functions ******************************/
void HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

252
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rcc_ex.h
View file

@ -342,7 +342,7 @@ typedef struct
/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
* @{ * @{
*/ */
#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */ #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */
#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
/** /**
* @} * @}
@ -351,58 +351,58 @@ typedef struct
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
* @{ * @{
*/ */
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U) #define RCC_PERIPHCLK_USART1 0x00000001U
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U) #define RCC_PERIPHCLK_USART2 0x00000002U
#if defined(USART3) #if defined(USART3)
#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U) #define RCC_PERIPHCLK_USART3 0x00000004U
#endif #endif
#if defined(UART4) #if defined(UART4)
#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U) #define RCC_PERIPHCLK_UART4 0x00000008U
#endif #endif
#if defined(UART5) #if defined(UART5)
#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U) #define RCC_PERIPHCLK_UART5 0x00000010U
#endif #endif
#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U) #define RCC_PERIPHCLK_LPUART1 0x00000020U
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U) #define RCC_PERIPHCLK_I2C1 0x00000040U
#if defined(I2C2) #if defined(I2C2)
#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U) #define RCC_PERIPHCLK_I2C2 0x00000080U
#endif #endif
#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U) #define RCC_PERIPHCLK_I2C3 0x00000100U
#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U) #define RCC_PERIPHCLK_LPTIM1 0x00000200U
#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U) #define RCC_PERIPHCLK_LPTIM2 0x00000400U
#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U) #define RCC_PERIPHCLK_SAI1 0x00000800U
#if defined(SAI2) #if defined(SAI2)
#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U) #define RCC_PERIPHCLK_SAI2 0x00001000U
#endif #endif
#if defined(USB_OTG_FS) || defined(USB) #if defined(USB_OTG_FS) || defined(USB)
#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U) #define RCC_PERIPHCLK_USB 0x00002000U
#endif #endif
#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U) #define RCC_PERIPHCLK_ADC 0x00004000U
#if defined(SWPMI1) #if defined(SWPMI1)
#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U) #define RCC_PERIPHCLK_SWPMI1 0x00008000U
#endif #endif
#if defined(DFSDM1_Filter0) #if defined(DFSDM1_Filter0)
#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U) #define RCC_PERIPHCLK_DFSDM1 0x00010000U
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define RCC_PERIPHCLK_DFSDM1AUDIO ((uint32_t)0x00200000U) #define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#endif #endif
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U) #define RCC_PERIPHCLK_RTC 0x00020000U
#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U) #define RCC_PERIPHCLK_RNG 0x00040000U
#if defined(SDMMC1) #if defined(SDMMC1)
#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U) #define RCC_PERIPHCLK_SDMMC1 0x00080000U
#endif #endif
#if defined(I2C4) #if defined(I2C4)
#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U) #define RCC_PERIPHCLK_I2C4 0x00100000U
#endif #endif
#if defined(LTDC) #if defined(LTDC)
#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00400000U) #define RCC_PERIPHCLK_LTDC 0x00400000U
#endif #endif
#if defined(DSI) #if defined(DSI)
#define RCC_PERIPHCLK_DSI ((uint32_t)0x00800000U) #define RCC_PERIPHCLK_DSI 0x00800000U
#endif #endif
#if defined(OCTOSPI1) || defined(OCTOSPI2) #if defined(OCTOSPI1) || defined(OCTOSPI2)
#define RCC_PERIPHCLK_OSPI ((uint32_t)0x01000000U) #define RCC_PERIPHCLK_OSPI 0x01000000U
#endif #endif
/** /**
* @} * @}
@ -412,7 +412,7 @@ typedef struct
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
* @{ * @{
*/ */
#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
@ -423,7 +423,7 @@ typedef struct
/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
* @{ * @{
*/ */
#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
@ -435,7 +435,7 @@ typedef struct
/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
* @{ * @{
*/ */
#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
@ -448,7 +448,7 @@ typedef struct
/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
* @{ * @{
*/ */
#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
@ -461,7 +461,7 @@ typedef struct
/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
* @{ * @{
*/ */
#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
@ -473,7 +473,7 @@ typedef struct
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
* @{ * @{
*/ */
#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
@ -484,7 +484,7 @@ typedef struct
/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
* @{ * @{
*/ */
#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
/** /**
@ -495,7 +495,7 @@ typedef struct
/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
* @{ * @{
*/ */
#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
/** /**
@ -506,7 +506,7 @@ typedef struct
/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
* @{ * @{
*/ */
#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
/** /**
@ -517,7 +517,7 @@ typedef struct
/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
* @{ * @{
*/ */
#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
/** /**
@ -528,7 +528,7 @@ typedef struct
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
* @{ * @{
*/ */
#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) #define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U
#if defined(RCC_PLLSAI2_SUPPORT) #if defined(RCC_PLLSAI2_SUPPORT)
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0
@ -552,7 +552,7 @@ typedef struct
/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
* @{ * @{
*/ */
#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U) #define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0
#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
@ -571,7 +571,7 @@ typedef struct
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
* @{ * @{
*/ */
#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
@ -582,7 +582,7 @@ typedef struct
/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
* @{ * @{
*/ */
#define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
@ -595,9 +595,9 @@ typedef struct
* @{ * @{
*/ */
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U) /*!< HSI48 clock selected as SDMMC1 clock */ #define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */
#else #else
#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as SDMMC1 clock */ #define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */
#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */
@ -614,9 +614,9 @@ typedef struct
* @{ * @{
*/ */
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U) #define RCC_RNGCLKSOURCE_HSI48 0x00000000U
#else #else
#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U) #define RCC_RNGCLKSOURCE_NONE 0x00000000U
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
@ -630,9 +630,9 @@ typedef struct
* @{ * @{
*/ */
#if defined(RCC_HSI48_SUPPORT) #if defined(RCC_HSI48_SUPPORT)
#define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U) #define RCC_USBCLKSOURCE_HSI48 0x00000000U
#else #else
#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U) #define RCC_USBCLKSOURCE_NONE 0x00000000U
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
@ -645,7 +645,7 @@ typedef struct
/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
* @{ * @{
*/ */
#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U) #define RCC_ADCCLKSOURCE_NONE 0x00000000U
#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
@ -659,7 +659,7 @@ typedef struct
/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
* @{ * @{
*/ */
#define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) #define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U
#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
/** /**
* @} * @}
@ -670,7 +670,7 @@ typedef struct
/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
* @{ * @{
*/ */
#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) #define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL
#else #else
@ -684,7 +684,7 @@ typedef struct
/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source /** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source
* @{ * @{
*/ */
#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U
#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 #define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0
#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 #define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1
/** /**
@ -697,7 +697,7 @@ typedef struct
/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source /** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source
* @{ * @{
*/ */
#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 ((uint32_t)0x00000000U) #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U
#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0
#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1
#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR #define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR
@ -710,7 +710,7 @@ typedef struct
/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source /** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
* @{ * @{
*/ */
#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) #define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL #define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL
/** /**
* @} * @}
@ -721,7 +721,7 @@ typedef struct
/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source /** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source
* @{ * @{
*/ */
#define RCC_OSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U) #define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U
#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 #define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0
#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 #define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1
/** /**
@ -742,13 +742,13 @@ typedef struct
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{ * @{
*/ */
#define RCC_CRS_NONE ((uint32_t)0x00000000U) #define RCC_CRS_NONE 0x00000000U
#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U) #define RCC_CRS_TIMEOUT 0x00000001U
#define RCC_CRS_SYNCOK ((uint32_t)0x00000002U) #define RCC_CRS_SYNCOK 0x00000002U
#define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U) #define RCC_CRS_SYNCWARN 0x00000004U
#define RCC_CRS_SYNCERR ((uint32_t)0x00000008U) #define RCC_CRS_SYNCERR 0x00000008U
#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U) #define RCC_CRS_SYNCMISS 0x00000010U
#define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U) #define RCC_CRS_TRIMOVF 0x00000020U
/** /**
* @} * @}
*/ */
@ -756,7 +756,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{ * @{
*/ */
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/** /**
@ -766,7 +766,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
* @{ * @{
*/ */
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
@ -781,7 +781,7 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
* @{ * @{
*/ */
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/** /**
* @} * @}
@ -790,7 +790,7 @@ typedef struct
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
* @{ * @{
*/ */
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/** /**
* @} * @}
@ -799,7 +799,7 @@ typedef struct
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
* @{ * @{
*/ */
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */ #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */
/** /**
* @} * @}
*/ */
@ -807,7 +807,7 @@ typedef struct
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
* @{ * @{
*/ */
#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval. #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */ corresponds to a higher output frequency */
/** /**
@ -817,8 +817,8 @@ typedef struct
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
* @{ * @{
*/ */
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/** /**
* @} * @}
*/ */
@ -1341,10 +1341,10 @@ typedef struct
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))
#else #else
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** @brief Macro to get the SAI1 clock source. /** @brief Macro to get the SAI1 clock source.
@ -1361,9 +1361,9 @@ typedef struct
* *
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))
#else #else
#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#if defined(SAI2) #if defined(SAI2)
@ -1385,10 +1385,10 @@ typedef struct
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))
#else #else
#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** @brief Macro to get the SAI2 clock source. /** @brief Macro to get the SAI2 clock source.
@ -1399,9 +1399,9 @@ typedef struct
* @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))
#else #else
#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#endif /* SAI2 */ #endif /* SAI2 */
@ -1416,7 +1416,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
/** @brief Macro to get the I2C1 clock source. /** @brief Macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1424,7 +1424,7 @@ typedef struct
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
*/ */
#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
#if defined(I2C2) #if defined(I2C2)
@ -1438,7 +1438,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
/** @brief Macro to get the I2C2 clock source. /** @brief Macro to get the I2C2 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1446,7 +1446,7 @@ typedef struct
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
*/ */
#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
#endif /* I2C2 */ #endif /* I2C2 */
@ -1460,7 +1460,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
/** @brief Macro to get the I2C3 clock source. /** @brief Macro to get the I2C3 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1468,7 +1468,7 @@ typedef struct
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
*/ */
#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
#if defined(I2C4) #if defined(I2C4)
@ -1482,7 +1482,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
/** @brief Macro to get the I2C4 clock source. /** @brief Macro to get the I2C4 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1490,7 +1490,7 @@ typedef struct
* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
*/ */
#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))) #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
#endif /* I2C4 */ #endif /* I2C4 */
@ -1506,7 +1506,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
/** @brief Macro to get the USART1 clock source. /** @brief Macro to get the USART1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1515,7 +1515,7 @@ typedef struct
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
*/ */
#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
/** @brief Macro to configure the USART2 clock (USART2CLK). /** @brief Macro to configure the USART2 clock (USART2CLK).
* *
@ -1528,7 +1528,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
/** @brief Macro to get the USART2 clock source. /** @brief Macro to get the USART2 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1537,7 +1537,7 @@ typedef struct
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
*/ */
#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
#if defined(USART3) #if defined(USART3)
@ -1552,7 +1552,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
/** @brief Macro to get the USART3 clock source. /** @brief Macro to get the USART3 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1561,7 +1561,7 @@ typedef struct
* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
*/ */
#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
#endif /* USART3 */ #endif /* USART3 */
@ -1578,7 +1578,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
/** @brief Macro to get the UART4 clock source. /** @brief Macro to get the UART4 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1587,7 +1587,7 @@ typedef struct
* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
*/ */
#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
#endif /* UART4 */ #endif /* UART4 */
@ -1604,7 +1604,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
/** @brief Macro to get the UART5 clock source. /** @brief Macro to get the UART5 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1613,7 +1613,7 @@ typedef struct
* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
*/ */
#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
#endif /* UART5 */ #endif /* UART5 */
@ -1628,7 +1628,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
/** @brief Macro to get the LPUART1 clock source. /** @brief Macro to get the LPUART1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1637,7 +1637,7 @@ typedef struct
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
*/ */
#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
* *
@ -1650,7 +1650,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
/** @brief Macro to get the LPTIM1 clock source. /** @brief Macro to get the LPTIM1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1659,7 +1659,7 @@ typedef struct
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
*/ */
#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
* *
@ -1672,7 +1672,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
/** @brief Macro to get the LPTIM2 clock source. /** @brief Macro to get the LPTIM2 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1681,7 +1681,7 @@ typedef struct
* @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
*/ */
#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) #define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
#if defined(SDMMC1) #if defined(SDMMC1)
@ -1727,12 +1727,12 @@ typedef struct
else \ else \
{ \ { \
CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \
} \ } \
} while(0) } while(0)
#else #else
#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
#endif /* RCC_CCIPR2_SDMMCSEL */ #endif /* RCC_CCIPR2_SDMMCSEL */
/** @brief Macro to get the SDMMC1 clock. /** @brief Macro to get the SDMMC1 clock.
@ -1757,10 +1757,10 @@ typedef struct
*/ */
#if defined(RCC_CCIPR2_SDMMCSEL) #if defined(RCC_CCIPR2_SDMMCSEL)
#define __HAL_RCC_GET_SDMMC1_SOURCE() \ #define __HAL_RCC_GET_SDMMC1_SOURCE() \
((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))) ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
#else #else
#define __HAL_RCC_GET_SDMMC1_SOURCE() \ #define __HAL_RCC_GET_SDMMC1_SOURCE() \
((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
#endif /* RCC_CCIPR2_SDMMCSEL */ #endif /* RCC_CCIPR2_SDMMCSEL */
#endif /* SDMMC1 */ #endif /* SDMMC1 */
@ -1783,7 +1783,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
/** @brief Macro to get the RNG clock. /** @brief Macro to get the RNG clock.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1797,7 +1797,7 @@ typedef struct
* @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
*/ */
#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
#if defined(USB_OTG_FS) || defined(USB) #if defined(USB_OTG_FS) || defined(USB)
@ -1819,7 +1819,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
/** @brief Macro to get the USB clock source. /** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1833,7 +1833,7 @@ typedef struct
* @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
*/ */
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
#endif /* USB_OTG_FS || USB */ #endif /* USB_OTG_FS || USB */
@ -1849,7 +1849,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
/** @brief Macro to get the ADC clock source. /** @brief Macro to get the ADC clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1860,7 +1860,7 @@ typedef struct
@endif @endif
* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
*/ */
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) #define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
#if defined(SWPMI1) #if defined(SWPMI1)
@ -1872,14 +1872,14 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
/** @brief Macro to get the SWPMI1 clock source. /** @brief Macro to get the SWPMI1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
* @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
* @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
*/ */
#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) #define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
#endif /* SWPMI1 */ #endif /* SWPMI1 */
@ -1893,10 +1893,10 @@ typedef struct
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
#else #else
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** @brief Macro to get the DFSDM1 clock source. /** @brief Macro to get the DFSDM1 clock source.
@ -1905,9 +1905,9 @@ typedef struct
* @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))) #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))
#else #else
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))) #define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
@ -1921,7 +1921,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))
/** @brief Macro to get the DFSDM1 audio clock source. /** @brief Macro to get the DFSDM1 audio clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1929,7 +1929,7 @@ typedef struct
* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock
* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock
*/ */
#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))) #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
@ -1947,7 +1947,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ #define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (uint32_t)(__LTDC_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))
/** @brief Macro to get the LTDC clock source. /** @brief Macro to get the LTDC clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -1956,7 +1956,7 @@ typedef struct
* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock
* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock
*/ */
#define __HAL_RCC_GET_LTDC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))) #define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))
#endif /* LTDC */ #endif /* LTDC */
@ -1970,14 +1970,14 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))
/** @brief Macro to get the DSI clock source. /** @brief Macro to get the DSI clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
* @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
* @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock
*/ */
#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))) #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))
#endif /* DSI */ #endif /* DSI */
@ -1992,7 +1992,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))
/** @brief Macro to get the OctoSPI clock source. /** @brief Macro to get the OctoSPI clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
@ -2000,7 +2000,7 @@ typedef struct
* @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock
* @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock
*/ */
#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))) #define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))
#endif /* OCTOSPI1 || OCTOSPI2 */ #endif /* OCTOSPI1 || OCTOSPI2 */
@ -2203,7 +2203,7 @@ typedef struct
* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
*/ */
/* CRS IT Error Mask */ /* CRS IT Error Mask */
#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
@ -2247,7 +2247,7 @@ typedef struct
*/ */
/* CRS Flag Error Mask */ /* CRS Flag Error Mask */
#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \

68
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rng.h
View file

@ -83,7 +83,7 @@ typedef enum
/** /**
* @brief RNG Handle Structure definition * @brief RNG Handle Structure definition
*/ */
typedef struct typedef struct __RNG_HandleTypeDef
{ {
RNG_TypeDef *Instance; /*!< Register base address */ RNG_TypeDef *Instance; /*!< Register base address */
@ -95,10 +95,41 @@ typedef struct
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
__IO uint32_t ErrorCode; /*!< RNG Error code */
uint32_t RandomNumber; /*!< Last Generated RNG Data */ uint32_t RandomNumber; /*!< Last Generated RNG Data */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
}RNG_HandleTypeDef; }RNG_HandleTypeDef;
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL RNG Callback ID enumeration definition
*/
typedef enum
{
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
} HAL_RNG_CallbackIDTypeDef;
/**
* @brief HAL RNG Callback pointer definition
*/
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef * hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -139,6 +170,17 @@ typedef struct
*/ */
#endif /* defined(RNG_CR_CED) */ #endif /* defined(RNG_CR_CED) */
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
#define HAL_RNG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000001U) /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -152,7 +194,15 @@ typedef struct
* @param __HANDLE__: RNG Handle * @param __HANDLE__: RNG Handle
* @retval None * @retval None
*/ */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
/** /**
* @brief Enable the RNG peripheral. * @brief Enable the RNG peripheral.
@ -180,7 +230,6 @@ typedef struct
*/ */
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** /**
* @brief Clear the selected RNG flag status. * @brief Clear the selected RNG flag status.
* @param __HANDLE__: RNG handle * @param __HANDLE__: RNG handle
@ -191,8 +240,6 @@ typedef struct
*/ */
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ #define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
/** /**
* @brief Enable the RNG interrupt. * @brief Enable the RNG interrupt.
* @param __HANDLE__: RNG Handle * @param __HANDLE__: RNG Handle
@ -249,6 +296,16 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -272,10 +329,11 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
*/ */
/* Peripheral State functions **************************************************/ /* Peripheral State functions **************************************************/
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions /** @defgroup RNG_Exported_Functions_Group3 Peripheral State and Error functions
* @{ * @{
*/ */
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
/** /**
* @} * @}
*/ */

71
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_rtc.h
View file

@ -176,9 +176,9 @@ typedef struct
}RTC_AlarmTypeDef; }RTC_AlarmTypeDef;
/** /**
* @brief Time Handle Structure definition * @brief RTC Handle Structure definition
*/ */
typedef struct typedef struct __RTC_HandleTypeDef
{ {
RTC_TypeDef *Instance; /*!< Register base address */ RTC_TypeDef *Instance; /*!< Register base address */
@ -188,8 +188,60 @@ typedef struct
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
#if defined(RTC_TAMPER1_SUPPORT)
void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
#endif /* RTC_TAMPER1_SUPPORT */
void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
#if defined(RTC_TAMPER3_SUPPORT)
void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* RTC_TAMPER3_SUPPORT */
void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
}RTC_HandleTypeDef; }RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LPTIM Callback ID enumeration definition
*/
typedef enum
{
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
#if defined(RTC_TAMPER1_SUPPORT)
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
#endif /* RTC_TAMPER1_SUPPORT */
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
#endif /* RTC_TAMPER3_SUPPORT */
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
}HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -431,7 +483,15 @@ typedef struct
* @param __HANDLE__: RTC handle. * @param __HANDLE__: RTC handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/** /**
* @brief Disable the write protection for RTC registers. * @brief Disable the write protection for RTC registers.
@ -655,6 +715,13 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

378
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_sai.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_SAI_H #ifndef STM32L4xx_HAL_SAI_H
#define __STM32L4xx_HAL_SAI_H #define STM32L4xx_HAL_SAI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -75,8 +75,9 @@ typedef enum
typedef void (*SAIcallback)(void); typedef void (*SAIcallback)(void);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/** /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
* @brief SAI PDM Init structure definition * @brief SAI PDM Init structure definition
* @{
*/ */
typedef struct typedef struct
{ {
@ -86,6 +87,9 @@ typedef struct
uint32_t ClockEnable; /*!< Specifies which clock must be enabled. uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
} SAI_PdmInitTypeDef; } SAI_PdmInitTypeDef;
/**
* @}
*/
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
@ -103,17 +107,17 @@ typedef struct
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
for BlockA and BlockB for BlockA and BlockB
This parameter can be a value of @ref SAI_Block_SyncExt This parameter can be a value of @ref SAI_Block_SyncExt
@note: If both audio blocks of same SAI are used, this parameter has @note If both audio blocks of same SAI are used, this parameter has
to be set to the same value for each audio block */ to be set to the same value for each audio block */
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive This parameter can be a value of @ref SAI_Block_Output_Drive
@note this value has to be set before enabling the audio block @note This value has to be set before enabling the audio block
but after the audio block configuration. */ but after the audio block configuration. */
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider This parameter can be a value of @ref SAI_Block_NoDivider
@note: For STM32L4Rx/STM32L4Sx devices : @note For STM32L4Rx/STM32L4Sx devices :
If bit NOMCK in the SAI_xCR1 register is cleared, the frame length If bit NOMCK in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256. should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NOMCK in the SAI_xCR1 register is set, the frame length can If bit NOMCK in the SAI_xCR1 register is set, the frame length can
@ -184,7 +188,7 @@ typedef struct
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
This parameter must be a number between Min_Data = 8 and Max_Data = 256. This parameter must be a number between Min_Data = 8 and Max_Data = 256.
@note: If master clock MCLK_x pin is declared as an output, the frame length @note If master clock MCLK_x pin is declared as an output, the frame length
should be aligned to a number equal to power of 2 in order to keep should be aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock. */ in an audio frame, an integer number of MCLK pulses by bit Clock. */
@ -262,17 +266,47 @@ typedef struct __SAI_HandleTypeDef
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
__IO uint32_t ErrorCode; /*!< SAI Error code */ __IO uint32_t ErrorCode; /*!< SAI Error code */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
#endif
} SAI_HandleTypeDef; } SAI_HandleTypeDef;
/** /**
* @} * @}
*/ */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
/**
* @brief SAI callback ID enumeration definition
*/
typedef enum
{
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
} HAL_SAI_CallbackIDTypeDef;
/**
* @brief SAI callback pointer definition
*/
typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
#endif
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup SAI_Exported_Constants SAI Exported Constants /** @defgroup SAI_Exported_Constants SAI Exported Constants
* @{ * @{
*/ */
@ -280,15 +314,18 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Error_Code SAI Error Code /** @defgroup SAI_Error_Code SAI Error Code
* @{ * @{
*/ */
#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ #define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ #define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ #define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ #define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ #define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ #define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ #define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ #define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ #define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -296,9 +333,9 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_SyncExt SAI External synchronisation /** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{ * @{
*/ */
#define SAI_SYNCEXT_DISABLE 0 #define SAI_SYNCEXT_DISABLE 0U
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
/** /**
* @} * @}
*/ */
@ -306,11 +343,11 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Protocol SAI Supported protocol /** @defgroup SAI_Protocol SAI Supported protocol
* @{ * @{
*/ */
#define SAI_I2S_STANDARD 0 #define SAI_I2S_STANDARD 0U
#define SAI_I2S_MSBJUSTIFIED 1 #define SAI_I2S_MSBJUSTIFIED 1U
#define SAI_I2S_LSBJUSTIFIED 2 #define SAI_I2S_LSBJUSTIFIED 2U
#define SAI_PCM_LONG 3 #define SAI_PCM_LONG 3U
#define SAI_PCM_SHORT 4 #define SAI_PCM_SHORT 4U
/** /**
* @} * @}
*/ */
@ -318,10 +355,10 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Protocol_DataSize SAI protocol data size /** @defgroup SAI_Protocol_DataSize SAI protocol data size
* @{ * @{
*/ */
#define SAI_PROTOCOL_DATASIZE_16BIT 0 #define SAI_PROTOCOL_DATASIZE_16BIT 0U
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define SAI_PROTOCOL_DATASIZE_24BIT 2 #define SAI_PROTOCOL_DATASIZE_24BIT 2U
#define SAI_PROTOCOL_DATASIZE_32BIT 3 #define SAI_PROTOCOL_DATASIZE_32BIT 3U
/** /**
* @} * @}
*/ */
@ -329,16 +366,16 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
* @{ * @{
*/ */
#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) #define SAI_AUDIO_FREQUENCY_192K 192000U
#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) #define SAI_AUDIO_FREQUENCY_96K 96000U
#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) #define SAI_AUDIO_FREQUENCY_48K 48000U
#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) #define SAI_AUDIO_FREQUENCY_44K 44100U
#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) #define SAI_AUDIO_FREQUENCY_32K 32000U
#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) #define SAI_AUDIO_FREQUENCY_22K 22050U
#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) #define SAI_AUDIO_FREQUENCY_16K 16000U
#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) #define SAI_AUDIO_FREQUENCY_11K 11025U
#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) #define SAI_AUDIO_FREQUENCY_8K 8000U
#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) #define SAI_AUDIO_FREQUENCY_MCKDIV 0U
/** /**
* @} * @}
*/ */
@ -347,8 +384,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
* @{ * @{
*/ */
#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U) #define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR) #define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
/** /**
* @} * @}
*/ */
@ -356,8 +393,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
* @{ * @{
*/ */
#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1) #define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2) #define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
/** /**
* @} * @}
*/ */
@ -366,10 +403,10 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Mode SAI Block Mode /** @defgroup SAI_Block_Mode SAI Block Mode
* @{ * @{
*/ */
#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) #define SAI_MODEMASTER_TX 0x00000000U
#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) #define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) #define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) #define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
/** /**
* @} * @}
@ -378,9 +415,9 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Protocol SAI Block Protocol /** @defgroup SAI_Block_Protocol SAI Block Protocol
* @{ * @{
*/ */
#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) #define SAI_FREE_PROTOCOL 0x00000000U
#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) #define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) #define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
/** /**
* @} * @}
*/ */
@ -388,12 +425,12 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Data_Size SAI Block Data Size /** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{ * @{
*/ */
#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) #define SAI_DATASIZE_8 SAI_xCR1_DS_1
#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) #define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) #define SAI_DATASIZE_16 SAI_xCR1_DS_2
#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) #define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) #define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) #define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
/** /**
* @} * @}
*/ */
@ -401,8 +438,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
* @{ * @{
*/ */
#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) #define SAI_FIRSTBIT_MSB 0x00000000U
#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) #define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
/** /**
* @} * @}
*/ */
@ -410,8 +447,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
* @{ * @{
*/ */
#define SAI_CLOCKSTROBING_FALLINGEDGE 0 #define SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define SAI_CLOCKSTROBING_RISINGEDGE 1 #define SAI_CLOCKSTROBING_RISINGEDGE 1U
/** /**
* @} * @}
*/ */
@ -419,10 +456,10 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
* @{ * @{
*/ */
#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ #define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ #define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ #define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ #define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
/** /**
* @} * @}
*/ */
@ -430,8 +467,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
* @{ * @{
*/ */
#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) #define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) #define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
/** /**
* @} * @}
*/ */
@ -439,22 +476,21 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
* @{ * @{
*/ */
#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) #define SAI_MASTERDIVIDER_ENABLE 0x00000000U
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK) #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK
#else #else
#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** /**
* @} * @}
*/ */
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{ * @{
*/ */
#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) #define SAI_FS_STARTFRAME 0x00000000U
#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) #define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
/** /**
* @} * @}
*/ */
@ -462,8 +498,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
* @{ * @{
*/ */
#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) #define SAI_FS_ACTIVE_LOW 0x00000000U
#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) #define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
/** /**
* @} * @}
*/ */
@ -471,19 +507,18 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
* @{ * @{
*/ */
#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) #define SAI_FS_FIRSTBIT 0x00000000U
#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) #define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
/** /**
* @} * @}
*/ */
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{ * @{
*/ */
#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) #define SAI_SLOTSIZE_DATASIZE 0x00000000U
#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) #define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) #define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
/** /**
* @} * @}
*/ */
@ -491,24 +526,24 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
* @{ * @{
*/ */
#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) #define SAI_SLOT_NOTACTIVE 0x00000000U
#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) #define SAI_SLOTACTIVE_0 0x00000001U
#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) #define SAI_SLOTACTIVE_1 0x00000002U
#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) #define SAI_SLOTACTIVE_2 0x00000004U
#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) #define SAI_SLOTACTIVE_3 0x00000008U
#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) #define SAI_SLOTACTIVE_4 0x00000010U
#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) #define SAI_SLOTACTIVE_5 0x00000020U
#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) #define SAI_SLOTACTIVE_6 0x00000040U
#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) #define SAI_SLOTACTIVE_7 0x00000080U
#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) #define SAI_SLOTACTIVE_8 0x00000100U
#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) #define SAI_SLOTACTIVE_9 0x00000200U
#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) #define SAI_SLOTACTIVE_10 0x00000400U
#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) #define SAI_SLOTACTIVE_11 0x00000800U
#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) #define SAI_SLOTACTIVE_12 0x00001000U
#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) #define SAI_SLOTACTIVE_13 0x00002000U
#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) #define SAI_SLOTACTIVE_14 0x00004000U
#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) #define SAI_SLOTACTIVE_15 0x00008000U
#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) #define SAI_SLOTACTIVE_ALL 0x0000FFFFU
/** /**
* @} * @}
*/ */
@ -516,8 +551,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
* @{ * @{
*/ */
#define SAI_STEREOMODE ((uint32_t)0x00000000U) #define SAI_STEREOMODE 0x00000000U
#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) #define SAI_MONOMODE SAI_xCR1_MONO
/** /**
* @} * @}
*/ */
@ -525,8 +560,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_TRIState_Management SAI TRIState Management /** @defgroup SAI_TRIState_Management SAI TRIState Management
* @{ * @{
*/ */
#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) #define SAI_OUTPUT_NOTRELEASED 0x00000000U
#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) #define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
/** /**
* @} * @}
*/ */
@ -534,11 +569,11 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
* @{ * @{
*/ */
#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) #define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) #define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) #define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) #define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) #define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
/** /**
* @} * @}
*/ */
@ -546,11 +581,11 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
* @{ * @{
*/ */
#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) #define SAI_NOCOMPANDING 0x00000000U
#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) #define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) #define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) #define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) #define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
/** /**
* @} * @}
*/ */
@ -558,8 +593,8 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
* @{ * @{
*/ */
#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) #define SAI_ZERO_VALUE 0x00000000U
#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) #define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
/** /**
* @} * @}
*/ */
@ -567,13 +602,13 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
* @{ * @{
*/ */
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) #define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) #define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) #define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) #define SAI_IT_FREQ SAI_xIMR_FREQIE
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) #define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) #define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) #define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
/** /**
* @} * @}
*/ */
@ -581,13 +616,13 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
* @{ * @{
*/ */
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) #define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) #define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) #define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) #define SAI_FLAG_FREQ SAI_xSR_FREQ
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) #define SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) #define SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) #define SAI_FLAG_LFSDET SAI_xSR_LFSDET
/** /**
* @} * @}
*/ */
@ -595,12 +630,12 @@ typedef struct __SAI_HandleTypeDef
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
* @{ * @{
*/ */
#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) #define SAI_FIFOSTATUS_EMPTY 0x00000000U
#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) #define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) #define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) #define SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) #define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) #define SAI_FIFOSTATUS_FULL 0x00050000U
/** /**
* @} * @}
*/ */
@ -610,21 +645,28 @@ typedef struct __SAI_HandleTypeDef
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup SAI_Exported_Macros SAI Exported Macros /** @defgroup SAI_Exported_Macros SAI Exported Macros
* @brief macros to handle interrupts and specific configurations * @brief macros to handle interrupts and specific configurations
* @{ * @{
*/ */
/** @brief Reset SAI handle state. /** @brief Reset SAI handle state.
* @param __HANDLE__: specifies the SAI Handle. * @param __HANDLE__ specifies the SAI Handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SAI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
#endif
/** @brief Enable or disable the specified SAI interrupts. /** @brief Enable the specified SAI interrupts.
* @param __HANDLE__: specifies the SAI Handle. * @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable. * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
@ -636,11 +678,25 @@ typedef struct __SAI_HandleTypeDef
* @retval None * @retval None
*/ */
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
/** @brief Disable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval None
*/
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SAI interrupt source is enabled or not. /** @brief Check whether the specified SAI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SAI Handle. * @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__: specifies the SAI interrupt source to check. * @param __INTERRUPT__ specifies the SAI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable
@ -654,8 +710,8 @@ typedef struct __SAI_HandleTypeDef
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SAI flag is set or not. /** @brief Check whether the specified SAI flag is set or not.
* @param __HANDLE__: specifies the SAI Handle. * @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
* @arg SAI_FLAG_MUTEDET: Mute detection flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag.
@ -669,8 +725,8 @@ typedef struct __SAI_HandleTypeDef
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SAI pending flag. /** @brief Clear the specified SAI pending flag.
* @param __HANDLE__: specifies the SAI Handle. * @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
* @arg SAI_FLAG_MUTEDET: Clear Mute detection * @arg SAI_FLAG_MUTEDET: Clear Mute detection
@ -684,7 +740,16 @@ typedef struct __SAI_HandleTypeDef
*/ */
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
/** @brief Enable SAI.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
/** @brief Disable SAI.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
/** /**
@ -697,13 +762,11 @@ typedef struct __SAI_HandleTypeDef
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup SAI_Exported_Functions /** @addtogroup SAI_Exported_Functions
* @{ * @{
*/ */
/* Initialization/de-initialization functions ********************************/ /* Initialization/de-initialization functions ********************************/
/** @addtogroup SAI_Exported_Functions_Group1 /** @addtogroup SAI_Exported_Functions_Group1
* @{ * @{
*/ */
@ -713,12 +776,19 @@ HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
/* SAI callbacks register/unregister functions ********************************/
HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
HAL_SAI_CallbackIDTypeDef CallbackID,
pSAI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
HAL_SAI_CallbackIDTypeDef CallbackID);
#endif
/** /**
* @} * @}
*/ */
/* I/O operation functions ***************************************************/ /* I/O operation functions ***************************************************/
/** @addtogroup SAI_Exported_Functions_Group2 /** @addtogroup SAI_Exported_Functions_Group2
* @{ * @{
*/ */
@ -839,7 +909,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
((VALUE) == SAI_LAST_SENT_VALUE)) ((VALUE) == SAI_LAST_SENT_VALUE))
@ -864,13 +934,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
((SIZE) == SAI_SLOTSIZE_16B) || \ ((SIZE) == SAI_SLOTSIZE_16B) || \
((SIZE) == SAI_SLOTSIZE_32B)) ((SIZE) == SAI_SLOTSIZE_32B))
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
@ -883,9 +953,9 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15)
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
/** /**
* @} * @}
@ -912,6 +982,6 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
} }
#endif #endif
#endif /* __STM32L4xx_HAL_SAI_H */ #endif /* STM32L4xx_HAL_SAI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_sai_ex.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_SAI_EX_H #ifndef STM32L4xx_HAL_SAI_EX_H
#define __STM32L4xx_HAL_SAI_EX_H #define STM32L4xx_HAL_SAI_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -55,7 +55,6 @@
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup SAIEx_Exported_Types SAIEx Exported Types /** @defgroup SAIEx_Exported_Types SAIEx Exported Types
* @{ * @{
*/ */
@ -82,7 +81,6 @@ typedef struct
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions /** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
* @{ * @{
*/ */
@ -90,9 +88,7 @@ typedef struct
/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
/** /**
* @} * @}
*/ */
@ -102,13 +98,10 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros /** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
* @{ * @{
*/ */
#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) #define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
/** /**
* @} * @}
*/ */
@ -127,6 +120,6 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
} }
#endif #endif
#endif /* __STM32L4xx_HAL_SAI_EX_H */ #endif /* STM32L4xx_HAL_SAI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

94
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_sd.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_SD_H #ifndef STM32L4xx_HAL_SD_H
#define __STM32L4xx_HAL_SD_H #define STM32L4xx_HAL_SD_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -133,7 +133,7 @@ typedef struct
/** /**
* @brief SD handle Structure definition * @brief SD handle Structure definition
*/ */
typedef struct typedef struct __SD_HandleTypeDef
{ {
SD_TypeDef *Instance; /*!< SD registers base address */ SD_TypeDef *Instance; /*!< SD registers base address */
@ -141,11 +141,11 @@ typedef struct
HAL_LockTypeDef Lock; /*!< SD locking object */ HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */ uint32_t TxXferSize; /*!< SD Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */ uint32_t RxXferSize; /*!< SD Rx Transfer size */
@ -168,6 +168,23 @@ typedef struct
uint32_t CID[4]; /*!< SD card identification number table */ uint32_t CID[4]; /*!< SD card identification number table */
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd);
void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd);
void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);
#endif
void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd);
void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd);
#endif
}SD_HandleTypeDef; }SD_HandleTypeDef;
/** /**
@ -208,7 +225,7 @@ typedef struct
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */ __IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */ __IO uint8_t FileFormatGroup; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
@ -264,6 +281,41 @@ typedef struct
* @} * @}
*/ */
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */
HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */
HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */
HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */
HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */
HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */
HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */
#endif
HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */
HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */
}HAL_SD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition
* @{
*/
typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
#endif
/**
* @}
*/
#endif
/** /**
* @} * @}
*/ */
@ -315,6 +367,10 @@ typedef struct
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ #define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -370,6 +426,19 @@ typedef struct
* @brief macros to handle interrupts and specific clock configurations * @brief macros to handle interrupts and specific clock configurations
* @{ * @{
*/ */
/** @brief Reset SD handle state.
* @param __HANDLE__ : SD handle.
* @retval None
*/
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET)
#endif
#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
/** /**
@ -672,6 +741,17 @@ void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd);
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
/* SD callback registering/unregistering */
HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);
#endif
#endif
/** /**
* @} * @}
*/ */
@ -798,6 +878,6 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
#endif #endif
#endif /* __STM32L4xx_HAL_SD_H */ #endif /* STM32L4xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_sd_ex.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_SD_EX_H #ifndef STM32L4xx_HAL_SD_EX_H
#define __STM32L4xx_HAL_SD_EX_H #define STM32L4xx_HAL_SD_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -139,6 +139,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
#endif #endif
#endif /* __STM32L4xx_HAL_SDEx_H */ #endif /* STM32L4xx_HAL_SDEx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

261
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smartcard.h
View file

@ -224,20 +224,6 @@ typedef enum
Value is allowed for gState only */ Value is allowed for gState only */
} HAL_SMARTCARD_StateTypeDef; } HAL_SMARTCARD_StateTypeDef;
/**
* @brief HAL SMARTCARD Error Code structure definition
*/
typedef enum
{
HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */
HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */
HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */
HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */
HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */
HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */
}HAL_SMARTCARD_ErrorTypeDef;
/** /**
* @brief SMARTCARD handle Structure definition * @brief SMARTCARD handle Structure definition
*/ */
@ -266,7 +252,7 @@ typedef struct __SMARTCARD_HandleTypeDef
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
#endif #endif
@ -289,8 +275,58 @@ typedef struct __SMARTCARD_HandleTypeDef
uint32_t ErrorCode; /*!< SmartCard Error code */ uint32_t ErrorCode; /*!< SmartCard Error code */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */
void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
} SMARTCARD_HandleTypeDef; } SMARTCARD_HandleTypeDef;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMARTCARD Callback ID enumeration definition
*/
typedef enum
{
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */
HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
} HAL_SMARTCARD_CallbackIDTypeDef;
/**
* @brief HAL SMARTCARD Callback pointer definition
*/
typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** /**
* @brief SMARTCARD clock sources * @brief SMARTCARD clock sources
*/ */
@ -313,6 +349,23 @@ typedef enum
* @{ * @{
*/ */
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{ * @{
*/ */
@ -519,10 +572,19 @@ typedef enum
* @param __HANDLE__ SMARTCARD handle. * @param __HANDLE__ SMARTCARD handle.
* @retval None * @retval None
*/ */
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0) (__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** @brief Flush the Smartcard Data registers. /** @brief Flush the Smartcard Data registers.
* @param __HANDLE__ specifies the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle.
@ -532,7 +594,7 @@ typedef enum
do{ \ do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0) } while(0U)
/** @brief Clear the specified SMARTCARD pending flag. /** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle.
@ -774,13 +836,133 @@ typedef enum
* @{ * @{
*/ */
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined (STM32L432xx) || defined (STM32L442xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#else
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#endif /* STM32L432xx || STM32L442xx */
/** @brief Check the Baud rate range. /** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on L4 (80 MHz) * @note The maximum Baud Rate is derived from the maximum clock on L4 (120 MHz)
* divided by the oversampling used on the SMARTCARD (i.e. 16). * divided by the oversampling used on the SMARTCARD (i.e. 16).
* @param __BAUDRATE__ Baud rate set by the configuration function. * @param __BAUDRATE__ Baud rate set by the configuration function.
* @retval Test result (TRUE or FALSE) * @retval Test result (TRUE or FALSE)
*/ */
#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 5000001) #define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 7500001U)
/** @brief Check the block length range. /** @brief Check the block length range.
* @note The maximum SMARTCARD block length is 0xFF. * @note The maximum SMARTCARD block length is 0xFF.
@ -879,6 +1061,7 @@ typedef enum
#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ #define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
#if defined(USART_PRESC_PRESCALER)
/** /**
* @brief Ensure that SMARTCARD clock Prescaler is valid. * @brief Ensure that SMARTCARD clock Prescaler is valid.
* @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
@ -896,38 +1079,7 @@ typedef enum
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
#endif
/**
* @brief Ensure that SMARTCARD FIFO mode is valid.
* @param __STATE__ SMARTCARD FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
/**
* @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
/** /**
* @brief Ensure that SMARTCARD advanced features initialization is valid. * @brief Ensure that SMARTCARD advanced features initialization is valid.
@ -1030,6 +1182,12 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1065,7 +1223,6 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard
* @} * @}
*/ */
/* Peripheral Control functions ***********************************************/
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group4 /** @addtogroup SMARTCARD_Exported_Functions_Group4
* @{ * @{

221
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smartcard_ex.h
View file

@ -89,6 +89,16 @@
*/ */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
* @brief SMARTCARD FIFO mode
* @{
*/
#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level /** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level
* @brief SMARTCARD TXFIFO level * @brief SMARTCARD TXFIFO level
* @{ * @{
@ -190,7 +200,7 @@
#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ #define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ #define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
#endif #endif /* USART_TCBGT_SUPPORT */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ #define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */
@ -207,7 +217,7 @@
*/ */
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise detected clear flag */ #define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ #define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
@ -216,7 +226,7 @@
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ #define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
#endif #endif /* USART_TCBGT_SUPPORT */
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
/** /**
@ -226,152 +236,12 @@
/** /**
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Constants SMARTCARDEx Private Constants
* @{
*/
#if defined(USART_CR1_FIFOEN)
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
* @{
*/
#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros /** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{ * @{
*/ */
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__: output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined (STM32L432xx) || defined (STM32L442xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#else
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} while(0)
#endif /* STM32L432xx || STM32L442xx */
/** @brief Set the Transmission Completion flag /** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
@ -390,13 +260,13 @@
{ \ { \
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
} \ } \
} while(0) } while(0U)
#else #else
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ #define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
do { \ do { \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} while(0) } while(0U)
#endif #endif /* USART_TCBGT_SUPPORT */
/** @brief Return the transmission completion flag. /** @brief Return the transmission completion flag.
* @param __HANDLE__ specifies the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle.
@ -410,7 +280,7 @@
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
#else #else
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) #define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
#endif #endif /* USART_TCBGT_SUPPORT */
/** /**
@ -423,7 +293,39 @@
((__TXCOMPLETE__) == SMARTCARD_TC)) ((__TXCOMPLETE__) == SMARTCARD_TC))
#else #else
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC) #define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
#endif #endif /* USART_TCBGT_SUPPORT */
/**
* @brief Ensure that SMARTCARD FIFO mode is valid.
* @param __STATE__ SMARTCARD FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
/**
* @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
/** /**
* @} * @}
@ -435,6 +337,23 @@
*/ */
/* Initialization and de-initialization functions ****************************/ /* Initialization and de-initialization functions ****************************/
/* IO operation methods *******************************************************/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ***********************************************/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 /** @addtogroup SMARTCARDEx_Exported_Functions_Group2
* @{ * @{
*/ */
@ -449,17 +368,11 @@ void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
* @} * @}
*/ */
/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 /** @addtogroup SMARTCARDEx_Exported_Functions_Group3
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);

70
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_smbus.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_SMBUS_H #ifndef STM32L4xx_HAL_SMBUS_H
#define __STM32L4xx_HAL_SMBUS_H #define STM32L4xx_HAL_SMBUS_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -136,6 +136,10 @@ typedef struct
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/** /**
* @} * @}
*/ */
@ -144,7 +148,7 @@ typedef struct
* @brief SMBUS handle Structure definition * @brief SMBUS handle Structure definition
* @{ * @{
*/ */
typedef struct typedef struct __SMBUS_HandleTypeDef
{ {
I2C_TypeDef *Instance; /*!< SMBUS registers base address */ I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@ -166,7 +170,47 @@ typedef struct
__IO uint32_t ErrorCode; /*!< SMBUS Error code */ __IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef; } SMBUS_HandleTypeDef;
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMBUS Callback ID enumeration definition
*/
typedef enum
{
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
} HAL_SMBUS_CallbackIDTypeDef;
/**
* @brief HAL SMBUS Callback pointer definition
*/
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -373,7 +417,15 @@ typedef struct
* @param __HANDLE__ specifies the SMBUS Handle. * @param __HANDLE__ specifies the SMBUS Handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif
/** @brief Enable the specified SMBUS interrupts. /** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle. * @param __HANDLE__ specifies the SMBUS Handle.
@ -590,7 +642,7 @@ typedef struct
* @{ * @{
*/ */
/* Initialization and de-initialization functions **********************************/ /* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
@ -598,6 +650,14 @@ void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -694,6 +754,6 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
#endif #endif
#endif /* __STM32L4xx_HAL_SMBUS_H */ #endif /* STM32L4xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

267
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_spi.h
View file

@ -163,8 +163,46 @@ typedef struct __SPI_HandleTypeDef
__IO uint32_t ErrorCode; /*!< SPI Error code */ __IO uint32_t ErrorCode; /*!< SPI Error code */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef; } SPI_HandleTypeDef;
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL SPI Callback ID enumeration definition
*/
typedef enum
{
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
} HAL_SPI_CallbackIDTypeDef;
/**
* @brief HAL SPI Callback pointer definition
*/
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -185,6 +223,9 @@ typedef struct __SPI_HandleTypeDef
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -396,16 +437,24 @@ typedef struct __SPI_HandleTypeDef
*/ */
/** @brief Reset SPI handle state. /** @brief Reset SPI handle state.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif
/** @brief Enable the specified SPI interrupts. /** @brief Enable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the interrupt source to enable. * @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@ -415,9 +464,9 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts. /** @brief Disable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI handle. * @param __HANDLE__ specifies the SPI handle.
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the interrupt source to disable. * @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@ -427,9 +476,9 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not. /** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the SPI interrupt source to check. * @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@ -439,9 +488,9 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not. /** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag
@ -457,14 +506,14 @@ typedef struct __SPI_HandleTypeDef
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag. /** @brief Clear the SPI CRCERR pending flag.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag. /** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
@ -477,7 +526,7 @@ typedef struct __SPI_HandleTypeDef
} while(0U) } while(0U)
/** @brief Clear the SPI OVR pending flag. /** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
@ -490,7 +539,7 @@ typedef struct __SPI_HandleTypeDef
} while(0U) } while(0U)
/** @brief Clear the SPI FRE pending flag. /** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
@ -502,14 +551,14 @@ typedef struct __SPI_HandleTypeDef
}while(0U) }while(0U)
/** @brief Enable the SPI peripheral. /** @brief Enable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral. /** @brief Disable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
@ -525,92 +574,168 @@ typedef struct __SPI_HandleTypeDef
*/ */
/** @brief Set the SPI transmit-only mode. /** @brief Set the SPI transmit-only mode.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode. /** @brief Set the SPI receive-only mode.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI. /** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__: specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None * @retval None
*/ */
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ /** @brief Checks if SPI Mode parameter is in allowed range.
((MODE) == SPI_MODE_MASTER)) * @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ /** @brief Checks if SPI Direction Mode parameter is in allowed range.
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ * @param __MODE__ specifies the SPI Direction Mode.
((MODE) == SPI_DIRECTION_1LINE)) * This parameter can be a value of @ref SPI_Direction
* @retval None
*/
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
((__MODE__) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) /** @brief Checks if SPI Direction Mode parameter is 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
((MODE) == SPI_DIRECTION_1LINE)) * @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_1LINE))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ /** @brief Checks if SPI Data Size parameter is in allowed range.
((DATASIZE) == SPI_DATASIZE_15BIT) || \ * @param __DATASIZE__ specifies the SPI Data Size.
((DATASIZE) == SPI_DATASIZE_14BIT) || \ * This parameter can be a value of @ref SPI_Data_Size
((DATASIZE) == SPI_DATASIZE_13BIT) || \ * @retval None
((DATASIZE) == SPI_DATASIZE_12BIT) || \ */
((DATASIZE) == SPI_DATASIZE_11BIT) || \ #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_10BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_9BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
((DATASIZE) == SPI_DATASIZE_7BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
((DATASIZE) == SPI_DATASIZE_6BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \ ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT)) ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
((__DATASIZE__) == SPI_DATASIZE_4BIT))
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ /** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
((CPOL) == SPI_POLARITY_HIGH)) * @param __CPOL__ specifies the SPI serial clock steady state.
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ /** @brief Checks if SPI Clock Phase parameter is in allowed range.
((CPHA) == SPI_PHASE_2EDGE)) * @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ /** @brief Checks if SPI Slave Select parameter is in allowed range.
((NSS) == SPI_NSS_HARD_INPUT) || \ * @param __NSS__ specifies the SPI Slave Slelect management parameter.
((NSS) == SPI_NSS_HARD_OUTPUT)) * This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ /** @brief Checks if SPI NSS Pulse parameter is in allowed range.
((NSSP) == SPI_NSS_PULSE_DISABLE)) * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
* This parameter can be a value of @ref SPI_NSSP_Mode
* @retval None
*/
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ * @retval None
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ */
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
((BIT) == SPI_FIRSTBIT_LSB)) * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ /** @brief Checks if SPI TI mode parameter is in allowed range.
((MODE) == SPI_TIMODE_ENABLE)) * @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE))
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ /** @brief Checks if SPI CRC calculation enabled state is in allowed range.
((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
* This parameter can be a value of @ref SPI_CRC_Calculation
* @retval None
*/
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\ /** @brief Checks if SPI CRC length is in allowed range.
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ * @param __LENGTH__ specifies the SPI CRC length.
((LENGTH) == SPI_CRC_LENGTH_16BIT)) * This parameter can be a value of @ref SPI_CRC_length
* @retval None
*/
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL) * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
* @retval None
*/
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
/** /**
* @} * @}
@ -632,6 +757,12 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

33
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_sram.h
View file

@ -41,9 +41,7 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ #if defined(FMC_BANK1)
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_ll_fmc.h" #include "stm32l4xx_ll_fmc.h"
@ -51,7 +49,6 @@
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup SRAM /** @addtogroup SRAM
* @{ * @{
*/ */
@ -66,12 +63,11 @@
*/ */
typedef enum typedef enum
{ {
HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
}HAL_SRAM_StateTypeDef; }HAL_SRAM_StateTypeDef;
/** /**
@ -90,7 +86,6 @@ typedef struct
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
}SRAM_HandleTypeDef; }SRAM_HandleTypeDef;
/** /**
@ -104,8 +99,8 @@ typedef struct
* @{ * @{
*/ */
/** @brief Reset SRAM handle state. /** @brief Reset SRAM handle state
* @param __HANDLE__: SRAM handle * @param __HANDLE__ SRAM handle
* @retval None * @retval None
*/ */
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
@ -129,9 +124,6 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
@ -150,6 +142,9 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
@ -170,7 +165,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
* @{ * @{
*/ */
/* SRAM Peripheral State functions ********************************************/ /* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/** /**
@ -189,9 +184,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
* @} * @}
*/ */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* FMC_BANK1 */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#ifdef __cplusplus #ifdef __cplusplus
} }

227
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_swpmi.h
View file

@ -41,10 +41,6 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
@ -52,6 +48,8 @@
* @{ * @{
*/ */
#if defined(SWPMI1)
/** @addtogroup SWPMI /** @addtogroup SWPMI
* @{ * @{
*/ */
@ -102,36 +100,67 @@ typedef enum
/** /**
* @brief SWPMI handle Structure definition * @brief SWPMI handle Structure definition
*/ */
typedef struct typedef struct __SWPMI_HandleTypeDef
{ {
SWPMI_TypeDef *Instance; /* SWPMI registers base address */ SWPMI_TypeDef *Instance; /*!< SWPMI registers base address */
SWPMI_InitTypeDef Init; /* SWMPI communication parameters */ SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */
uint32_t *pTxBuffPtr; /* Pointer to SWPMI Tx transfer Buffer */ uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */
uint32_t TxXferSize; /* SWPMI Tx Transfer size */ uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */
uint32_t TxXferCount; /* SWPMI Tx Transfer Counter */ uint32_t TxXferCount; /*!< SWPMI Tx Transfer Counter */
uint32_t *pRxBuffPtr; /* Pointer to SWPMI Rx transfer Buffer */ uint32_t *pRxBuffPtr; /*!< Pointer to SWPMI Rx transfer Buffer */
uint32_t RxXferSize; /* SWPMI Rx Transfer size */ uint32_t RxXferSize; /*!< SWPMI Rx Transfer size */
uint32_t RxXferCount; /* SWPMI Rx Transfer Counter */ uint32_t RxXferCount; /*!< SWPMI Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /* SWPMI Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmatx; /*!< SWPMI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /* SWPMI Rx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< SWPMI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /* SWPMI object */ HAL_LockTypeDef Lock; /*!< SWPMI object */
__IO HAL_SWPMI_StateTypeDef State; /* SWPMI communication state */ __IO HAL_SWPMI_StateTypeDef State; /*!< SWPMI communication state */
__IO uint32_t ErrorCode; /* SWPMI Error code */ __IO uint32_t ErrorCode; /*!< SWPMI Error code */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
#endif
}SWPMI_HandleTypeDef; }SWPMI_HandleTypeDef;
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
/**
* @brief SWPMI callback ID enumeration definition
*/
typedef enum
{
HAL_SWPMI_RX_COMPLETE_CB_ID = 0x00U, /*!< SWPMI receive complete callback ID */
HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SWPMI receive half complete callback ID */
HAL_SWPMI_TX_COMPLETE_CB_ID = 0x02U, /*!< SWPMI transmit complete callback ID */
HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SWPMI transmit half complete callback ID */
HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */
HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */
HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */
}HAL_SWPMI_CallbackIDTypeDef;
/**
* @brief SWPMI callback pointer definition
*/
typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi);
#endif
/** /**
* @} * @}
*/ */
@ -150,6 +179,11 @@ typedef struct
#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */ #define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */ #define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */
#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */ #define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_SWPMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Transfer timeout */
#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT ((uint32_t)0x00000040) /*!< End Tx buffer timeout */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
#define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */
#endif
/** /**
* @} * @}
*/ */
@ -231,123 +265,131 @@ typedef struct
*/ */
/** @brief Reset SWPMI handle state. /** @brief Reset SWPMI handle state.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
#endif
/** /**
* @brief Enable the SWPMI peripheral. * @brief Enable the SWPMI peripheral.
* @param __HANDLE__: SWPMI handle * @param __HANDLE__ SWPMI handle
* @retval None * @retval None
*/ */
#define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) #define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
/** /**
* @brief Disable the SWPMI peripheral. * @brief Disable the SWPMI peripheral.
* @param __HANDLE__: SWPMI handle * @param __HANDLE__ SWPMI handle
* @retval None * @retval None
*/ */
#define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT) #define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
/** @brief Check whether the specified SWPMI flag is set or not. /** @brief Check whether the specified SWPMI flag is set or not.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. * @arg SWPMI_FLAG_RXBFF Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag.
* @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. * @arg SWPMI_FLAG_RXBERF Receive CRC error flag.
* @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag.
* @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag.
* @arg SWPMI_FLAG_RXNE : Receive data register not empty. * @arg SWPMI_FLAG_RXNE Receive data register not empty.
* @arg SWPMI_FLAG_TXE : Transmit data register empty. * @arg SWPMI_FLAG_TXE Transmit data register empty.
* @arg SWPMI_FLAG_TCF : Transfer complete flag. * @arg SWPMI_FLAG_TCF Transfer complete flag.
* @arg SWPMI_FLAG_SRF : Slave resume flag. * @arg SWPMI_FLAG_SRF Slave resume flag.
* @arg SWPMI_FLAG_SUSP : SUSPEND flag. * @arg SWPMI_FLAG_SUSP SUSPEND flag.
* @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag. * @arg SWPMI_FLAG_DEACTF DEACTIVATED flag.
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) #define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SWPMI ISR flag. /** @brief Clear the specified SWPMI ISR flag.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF : Receive buffer full flag. * @arg SWPMI_FLAG_RXBFF Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag. * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag.
* @arg SWPMI_FLAG_RXBERF : Receive CRC error flag. * @arg SWPMI_FLAG_RXBERF Receive CRC error flag.
* @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag. * @arg SWPMI_FLAG_RXOVRF Receive overrun error flag.
* @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag. * @arg SWPMI_FLAG_TXUNRF Transmit underrun error flag.
* @arg SWPMI_FLAG_TCF : Transfer complete flag. * @arg SWPMI_FLAG_TCF Transfer complete flag.
* @arg SWPMI_FLAG_SRF : Slave resume flag. * @arg SWPMI_FLAG_SRF Slave resume flag.
* @retval None * @retval None
*/ */
#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__)) #define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
/** @brief Enable the specified SWPMI interrupt. /** @brief Enable the specified SWPMI interrupt.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __INTERRUPT__: specifies the SWPMI interrupt source to enable. * @param __INTERRUPT__ specifies the SWPMI interrupt source to enable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt. * @arg SWPMI_IT_SRIE Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt. * @arg SWPMI_IT_TCIE Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt. * @arg SWPMI_IT_TIE Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt. * @arg SWPMI_IT_RIE Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt.
* @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt.
* @retval None * @retval None
*/ */
#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) #define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
/** @brief Disable the specified SWPMI interrupt. /** @brief Disable the specified SWPMI interrupt.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __INTERRUPT__: specifies the SWPMI interrupt source to disable. * @param __INTERRUPT__ specifies the SWPMI interrupt source to disable.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt. * @arg SWPMI_IT_SRIE Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt. * @arg SWPMI_IT_TCIE Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt. * @arg SWPMI_IT_TIE Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt. * @arg SWPMI_IT_RIE Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt.
* @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt. * @arg SWPMI_IT_RXBEIE Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt.
* @retval None * @retval None
*/ */
#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) #define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
/** @brief Check whether the specified SWPMI interrupt has occurred or not. /** @brief Check whether the specified SWPMI interrupt has occurred or not.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __IT__: specifies the SWPMI interrupt to check. * @param __IT__ specifies the SWPMI interrupt to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt. * @arg SWPMI_IT_SRIE Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt. * @arg SWPMI_IT_TCIE Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt. * @arg SWPMI_IT_TIE Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt. * @arg SWPMI_IT_RIE Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt.
* @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt.
* @retval The new state of __IT__ (TRUE or FALSE). * @retval The new state of __IT__ (TRUE or FALSE).
*/ */
#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__)) #define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
/** @brief Check whether the specified SWPMI interrupt source is enabled or not. /** @brief Check whether the specified SWPMI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SWPMI Handle. * @param __HANDLE__ specifies the SWPMI Handle.
* @param __IT__: specifies the SWPMI interrupt source to check. * @param __IT__ specifies the SWPMI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt. * @arg SWPMI_IT_SRIE Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt. * @arg SWPMI_IT_TCIE Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt. * @arg SWPMI_IT_TIE Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt. * @arg SWPMI_IT_RIE Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt. * @arg SWPMI_IT_TXUNRIE Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt. * @arg SWPMI_IT_RXOVRIE Receive overrun error interrupt.
* @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt. * @arg SWPMI_IT_RXBERIE Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt. * @arg SWPMI_IT_TXBEIE Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt. * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt.
* @retval The new state of __IT__ (TRUE or FALSE). * @retval The new state of __IT__ (TRUE or FALSE).
*/ */
#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) #define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
@ -366,6 +408,15 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
/* SWPMI callbacks register/unregister functions ********************************/
HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi,
HAL_SWPMI_CallbackIDTypeDef CallbackID,
pSWPMI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi,
HAL_SWPMI_CallbackIDTypeDef CallbackID);
#endif
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
@ -445,14 +496,12 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
* @} * @}
*/ */
#endif /* SWPMI1 */
/** /**
* @} * @}
*/ */
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

814
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim.h
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238
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tim_ex.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_TIM_EX_H #ifndef STM32L4xx_HAL_TIM_EX_H
#define __STM32L4xx_HAL_TIM_EX_H #define STM32L4xx_HAL_TIM_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -63,7 +63,6 @@
typedef struct typedef struct
{ {
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@ -80,7 +79,8 @@ typedef struct
/** /**
* @brief TIM Break/Break2 input configuration * @brief TIM Break/Break2 input configuration
*/ */
typedef struct { typedef struct
{
uint32_t Source; /*!< Specifies the source of the timer break input. uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */ This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
@ -88,7 +88,8 @@ typedef struct {
uint32_t Polarity; /*!< Specifies the break input source polarity. uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */ Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef; }
TIMEx_BreakInputConfigTypeDef;
/** /**
* @} * @}
@ -103,131 +104,98 @@ typedef struct {
/** @defgroup TIMEx_Remap TIM Extended Remapping /** @defgroup TIMEx_Remap TIM Extended Remapping
* @{ * @{
*/ */
#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ETR_ADC1_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR1_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR1_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (ADC3)
defined (STM32L496xx) || defined (STM32L4A6xx) #define TIM_TIM1_ETR_ADC3_NONE 0x00000000U /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ETR_ADC3_AWD1 TIM1_OR1_ETR_ADC3_RMP_0 /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ #define TIM_TIM1_ETR_ADC3_AWD2 TIM1_OR1_ETR_ADC3_RMP_1 /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ #define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* ADC3 */
/* STM32L496xx || STM32L4A6xx */ #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 TI1 is connected to GPIO */
#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM1_OR1_TI1_RMP /* !< TIM1 TI1 is connected to COMP1 */
#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_OR2_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (USB_OTG_FS)
defined (STM32L496xx) || defined (STM32L4A6xx) || \ #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM2_ITR1_OTG_FS_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to OTG_FS SOF */
#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ #else
#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ #if defined(STM32L471xx)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #define TIM_TIM2_ITR1_TIM8_TRGO 0x00000000U /* !< TIM2_ITR1 is connected to TIM8_TRGO */
/* STM32L496xx || STM32L4A6xx || */ #define TIM_TIM2_ITR1_NONE TIM2_OR1_ITR1_RMP /* !< No internal trigger on TIM2_ITR1 */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #else
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ #define TIM_TIM2_ITR1_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #define TIM_TIM2_ITR1_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ #endif /* STM32L471xx */
#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ #endif /* USB_OTG_FS */
#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */
/* STM32L451xx || STM32L452xx || STM32L462xx */ #define TIM_TIM2_ETR_LSE TIM2_OR1_ETR1_RMP /* !< TIM2_ETR is connected to LSE */
#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ #define TIM_TIM2_ETR_COMP1 TIM2_OR2_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ #define TIM_TIM2_ETR_COMP2 TIM2_OR2_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2 TI4 is connected to GPIO */
#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ #define TIM_TIM2_TI4_COMP1 TIM2_OR1_TI4_RMP_0 /* !< TIM2 TI4 is connected to COMP1 output */
#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ #define TIM_TIM2_TI4_COMP2 TIM2_OR1_TI4_RMP_1 /* !< TIM2 TI4 is connected to COMP2 output */
#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */
#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ #if defined (TIM3)
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3 TI1 is connected to GPIO */
defined (STM32L496xx) || defined (STM32L4A6xx) || \ #define TIM_TIM3_TI1_COMP1 TIM3_OR1_TI1_RMP_0 /* !< TIM3 TI1 is connected to COMP1 output */
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM3_TI1_COMP2 TIM3_OR1_TI1_RMP_1 /* !< TIM3 TI1 is connected to COMP2 output */
#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */
#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ #define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ #define TIM_TIM3_ETR_COMP1 TIM3_OR2_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ #endif /* TIM3 */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (TIM8)
defined (STM32L496xx) || defined (STM32L4A6xx) #if defined(ADC2) && defined(ADC3)
#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM8_ETR_ADC2_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ #define TIM_TIM8_ETR_ADC2_AWD1 TIM8_OR1_ETR_ADC2_RMP_0 /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ #define TIM_TIM8_ETR_ADC2_AWD2 TIM8_OR1_ETR_ADC2_RMP_1 /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM8_ETR_ADC3_NONE 0x00000000U /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD1 TIM8_OR1_ETR_ADC3_RMP_0 /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD2 TIM8_OR1_ETR_ADC3_RMP_1 /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* ADC2 && ADC3 */
/* STM32L496xx || STM32L4A6xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */
#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */
#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ #define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8 TI1 is connected to GPIO */
#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ #define TIM_TIM8_TI1_COMP2 TIM8_OR1_TI1_RMP /* !< TIM8 TI1 is connected to COMP1 */
#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM8_ETR_COMP1 TIM8_OR2_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 output */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ #define TIM_TIM8_ETR_COMP2 TIM8_OR2_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 output */
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #endif /* TIM8 */
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15 TI1 is connected to GPIO */
#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM15_TI1_LSE TIM15_OR1_TI1_RMP /* !< TIM15 TI1 is connected to LSE */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ #define TIM_TIM15_ENCODERMODE_NONE 0x00000000U /* !< No redirection */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #define TIM_TIM15_ENCODERMODE_TIM2 TIM15_OR1_ENCODER_MODE_0 /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
/* STM32L496xx || STM32L4A6xx || */ #if defined (TIM3)
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #define TIM_TIM15_ENCODERMODE_TIM3 TIM15_OR1_ENCODER_MODE_1 /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #endif /* TIM3 */
defined (STM32L496xx) || defined (STM32L4A6xx) || \ #if defined (TIM4)
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* TIM4 */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ #define TIM_TIM16_TI1_LSI TIM16_OR1_TI1_RMP_0 /* !< TIM16 TI1 is connected to LSI */
#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ #define TIM_TIM16_TI1_LSE TIM16_OR1_TI1_RMP_1 /* !< TIM16 TI1 is connected to LSE */
#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ #define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ #if defined (TIM16_OR1_TI1_RMP_2)
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ #define TIM_TIM16_TI1_MSI TIM16_OR1_TI1_RMP_2 /* !< TIM16 TI1 is connected to MSI */
defined (STM32L496xx) || defined (STM32L4A6xx)
#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */
#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ #define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */
#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ #define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */
#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ #endif /* TIM16_OR1_TI1_RMP_2 */
/* STM32L451xx || STM32L452xx || STM32L462xx || */
/* STM32L496xx || STM32L4A6xx */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (TIM17)
defined (STM32L496xx) || defined (STM32L4A6xx) || \ #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #define TIM_TIM17_TI1_MSI TIM17_OR1_TI1_RMP_0 /* !< TIM17 TI1 is connected to MSI */
#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ #define TIM_TIM17_TI1_HSE_32 TIM17_OR1_TI1_RMP_1 /* !< TIM17 TI1 is connected to HSE div 32 */
#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */
#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */
#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ #define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* TIM17 */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** /**
* @} * @}
*/ */
@ -235,8 +203,8 @@ typedef struct {
/** @defgroup TIMEx_Break_Input TIM Extended Break input /** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{ * @{
*/ */
#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ #define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ #define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
/** /**
* @} * @}
*/ */
@ -244,18 +212,12 @@ typedef struct {
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{ * @{
*/ */
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ #if defined (DFSDM1_Channel0)
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
defined (STM32L496xx) || defined (STM32L4A6xx) || \ #endif /* DFSDM1_Channel0 */
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** /**
* @} * @}
*/ */
@ -263,8 +225,8 @@ typedef struct {
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{ * @{
*/ */
#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
/** /**
* @} * @}
*/ */
@ -272,8 +234,8 @@ typedef struct {
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{ * @{
*/ */
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
/** /**
* @} * @}
*/ */
@ -302,10 +264,7 @@ typedef struct {
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ #if defined (DFSDM1_Channel0)
defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
@ -314,15 +273,14 @@ typedef struct {
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ #endif /* DFSDM1_Channel0 */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
/** /**
* @} * @}
*/ */
@ -425,7 +383,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_Bre
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/** /**
* @} * @}
*/ */
@ -437,6 +394,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
/* Extended Callback **********************************************************/ /* Extended Callback **********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
@ -479,6 +437,6 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
#endif #endif
#endif /* __STM32L4xx_HAL_TIM_EX_H */ #endif /* STM32L4xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

594
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_tsc.h
View file

@ -62,10 +62,10 @@
*/ */
typedef enum typedef enum
{ {
HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */ HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */ HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */ HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */ HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
} HAL_TSC_StateTypeDef; } HAL_TSC_StateTypeDef;
/** /**
@ -73,8 +73,8 @@ typedef enum
*/ */
typedef enum typedef enum
{ {
TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */ TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */ TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
} TSC_GroupStatusTypeDef; } TSC_GroupStatusTypeDef;
/** /**
@ -122,14 +122,69 @@ typedef struct
/** /**
* @brief TSC handle Structure definition * @brief TSC handle Structure definition
*/ */
typedef struct typedef struct __TSC_HandleTypeDef
{ {
TSC_TypeDef *Instance; /*!< Register base address */ TSC_TypeDef *Instance; /*!< Register base address */
TSC_InitTypeDef Init; /*!< Initialization parameters */ TSC_InitTypeDef Init; /*!< Initialization parameters */
__IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
HAL_LockTypeDef Lock; /*!< Lock feature */ HAL_LockTypeDef Lock; /*!< Lock feature */
__IO uint32_t ErrorCode; /*!< I2C Error code */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
} TSC_HandleTypeDef; } TSC_HandleTypeDef;
/**
* @brief TSC Group Index Structure definition
*/
typedef enum
{
TSC_GROUP1_IDX = 0x00U,
TSC_GROUP2_IDX,
TSC_GROUP3_IDX,
TSC_GROUP4_IDX,
#if defined(TSC_IOCCR_G5_IO1)
TSC_GROUP5_IDX,
#endif
#if defined(TSC_IOCCR_G6_IO1)
TSC_GROUP6_IDX,
#endif
#if defined(TSC_IOCCR_G7_IO1)
TSC_GROUP7_IDX,
#endif
#if defined(TSC_IOCCR_G8_IO1)
TSC_GROUP8_IDX,
#endif
TSC_NB_OF_GROUPS
}TSC_GroupIndexTypeDef;
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL TSC Callback ID enumeration definition
*/
typedef enum
{
HAL_TSC_CONV_COMPLETE_CB_ID = 0x00U, /*!< TSC Conversion completed callback ID */
HAL_TSC_ERROR_CB_ID = 0x01U, /*!< TSC Error callback ID */
HAL_TSC_MSPINIT_CB_ID = 0x02U, /*!< TSC Msp Init callback ID */
HAL_TSC_MSPDEINIT_CB_ID = 0x03U /*!< TSC Msp DeInit callback ID */
} HAL_TSC_CallbackIDTypeDef;
/**
* @brief HAL TSC Callback pointer definition
*/
typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -139,25 +194,37 @@ typedef struct
* @{ * @{
*/ */
/** @defgroup TSC_Error_Code_definition TSC Error Code definition
* @brief TSC Error Code definition
* @{
*/
#define HAL_TSC_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define HAL_TSC_ERROR_INVALID_CALLBACK (0x00000001U) /*!< Invalid Callback error */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length /** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{ * @{
*/ */
#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28)) #define TSC_CTPH_1CYCLE 0x00000000U /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28)) #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28)) #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28)) #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28)) #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28)) #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28)) #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28)) #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28)) #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28)) #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28)) #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28)) #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28)) #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28)) #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28)) #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28)) #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/** /**
* @} * @}
*/ */
@ -165,22 +232,22 @@ typedef struct
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{ * @{
*/ */
#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24)) #define TSC_CTPL_1CYCLE 0x00000000U /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24)) #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24)) #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24)) #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24)) #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24)) #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24)) #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24)) #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24)) #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24)) #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24)) #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24)) #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24)) #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24)) #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24)) #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24)) #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/** /**
* @} * @}
*/ */
@ -188,8 +255,8 @@ typedef struct
/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
* @{ * @{
*/ */
#define TSC_SS_PRESC_DIV1 ((uint32_t)0) #define TSC_SS_PRESC_DIV1 0x00000000U /*!< Spread Spectrum Prescaler Div1 */
#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC) #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
/** /**
* @} * @}
*/ */
@ -197,14 +264,14 @@ typedef struct
/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
* @{ * @{
*/ */
#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12)) #define TSC_PG_PRESC_DIV1 0x00000000U /*!< Pulse Generator HCLK Div1 */
#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12)) #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12)) #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12)) #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12)) #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12)) #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12)) #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12)) #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
/** /**
* @} * @}
*/ */
@ -212,13 +279,13 @@ typedef struct
/** @defgroup TSC_MaxCount_Value Max Count Value /** @defgroup TSC_MaxCount_Value Max Count Value
* @{ * @{
*/ */
#define TSC_MCV_255 ((uint32_t)(0 << 5)) #define TSC_MCV_255 0x00000000U /*!< 255 maximum number of charge transfer pulses */
#define TSC_MCV_511 ((uint32_t)(1 << 5)) #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
#define TSC_MCV_1023 ((uint32_t)(2 << 5)) #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
#define TSC_MCV_2047 ((uint32_t)(3 << 5)) #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
#define TSC_MCV_4095 ((uint32_t)(4 << 5)) #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
#define TSC_MCV_8191 ((uint32_t)(5 << 5)) #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
#define TSC_MCV_16383 ((uint32_t)(6 << 5)) #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
/** /**
* @} * @}
*/ */
@ -226,8 +293,8 @@ typedef struct
/** @defgroup TSC_IO_Default_Mode IO Default Mode /** @defgroup TSC_IO_Default_Mode IO Default Mode
* @{ * @{
*/ */
#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0) #define TSC_IODEF_OUT_PP_LOW 0x00000000U /*!< I/Os are forced to output push-pull low */
#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
/** /**
* @} * @}
*/ */
@ -235,8 +302,8 @@ typedef struct
/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
* @{ * @{
*/ */
#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) #define TSC_SYNC_POLARITY_FALLING 0x00000000U /*!< Falling edge only */
#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
/** /**
* @} * @}
*/ */
@ -244,19 +311,8 @@ typedef struct
/** @defgroup TSC_Acquisition_Mode Acquisition Mode /** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{ * @{
*/ */
#define TSC_ACQ_MODE_NORMAL ((uint32_t)0) #define TSC_ACQ_MODE_NORMAL 0x00000000U /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM) #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
/** @defgroup TSC_IO_Mode IO Mode
* @{
*/
#define TSC_IOMODE_UNUSED ((uint32_t)0)
#define TSC_IOMODE_CHANNEL ((uint32_t)1)
#define TSC_IOMODE_SHIELD ((uint32_t)2)
#define TSC_IOMODE_SAMPLING ((uint32_t)3)
/** /**
* @} * @}
*/ */
@ -264,8 +320,8 @@ typedef struct
/** @defgroup TSC_interrupts_definition Interrupts definition /** @defgroup TSC_interrupts_definition Interrupts definition
* @{ * @{
*/ */
#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE) #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE) #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
/** /**
* @} * @}
*/ */
@ -273,8 +329,8 @@ typedef struct
/** @defgroup TSC_flags_definition Flags definition /** @defgroup TSC_flags_definition Flags definition
* @{ * @{
*/ */
#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF) #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF) #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
/** /**
* @} * @}
*/ */
@ -282,76 +338,96 @@ typedef struct
/** @defgroup TSC_Group_definition Group definition /** @defgroup TSC_Group_definition Group definition
* @{ * @{
*/ */
#define TSC_NB_OF_GROUPS (8) #define TSC_GROUP1 (uint32_t)(0x1U << TSC_GROUP1_IDX)
#define TSC_GROUP2 (uint32_t)(0x1U << TSC_GROUP2_IDX)
#define TSC_GROUP3 (uint32_t)(0x1U << TSC_GROUP3_IDX)
#define TSC_GROUP4 (uint32_t)(0x1U << TSC_GROUP4_IDX)
#if defined(TSC_IOCCR_G5_IO1)
#define TSC_GROUP5 (uint32_t)(0x1U << TSC_GROUP5_IDX)
#endif
#if defined(TSC_IOCCR_G6_IO1)
#define TSC_GROUP6 (uint32_t)(0x1U << TSC_GROUP6_IDX)
#endif
#if defined(TSC_IOCCR_G7_IO1)
#define TSC_GROUP7 (uint32_t)(0x1U << TSC_GROUP7_IDX)
#endif
#if defined(TSC_IOCCR_G8_IO1)
#define TSC_GROUP8 (uint32_t)(0x1U << TSC_GROUP8_IDX)
#endif
#define TSC_GROUP1 ((uint32_t)0x00000001) #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000U /*!< TSC GroupX not supported */
#define TSC_GROUP2 ((uint32_t)0x00000002)
#define TSC_GROUP3 ((uint32_t)0x00000004)
#define TSC_GROUP4 ((uint32_t)0x00000008)
#define TSC_GROUP5 ((uint32_t)0x00000010)
#define TSC_GROUP6 ((uint32_t)0x00000020)
#define TSC_GROUP7 ((uint32_t)0x00000040)
#define TSC_GROUP8 ((uint32_t)0x00000080)
#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
#define TSC_GROUP1_IDX ((uint32_t)0) #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
#define TSC_GROUP2_IDX ((uint32_t)1) #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
#define TSC_GROUP3_IDX ((uint32_t)2) #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
#define TSC_GROUP4_IDX ((uint32_t)3) #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
#define TSC_GROUP5_IDX ((uint32_t)4)
#define TSC_GROUP6_IDX ((uint32_t)5)
#define TSC_GROUP7_IDX ((uint32_t)6)
#define TSC_GROUP8_IDX ((uint32_t)7)
#define TSC_GROUP1_IO1 ((uint32_t)0x00000001) #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
#define TSC_GROUP1_IO2 ((uint32_t)0x00000002) #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
#define TSC_GROUP1_IO3 ((uint32_t)0x00000004) #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
#define TSC_GROUP1_IO4 ((uint32_t)0x00000008) #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
#define TSC_GROUP2_IO1 ((uint32_t)0x00000010) #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
#define TSC_GROUP2_IO2 ((uint32_t)0x00000020) #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
#define TSC_GROUP2_IO3 ((uint32_t)0x00000040) #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
#define TSC_GROUP2_IO4 ((uint32_t)0x00000080) #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
#define TSC_GROUP3_IO1 ((uint32_t)0x00000100) #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
#define TSC_GROUP3_IO2 ((uint32_t)0x00000200) #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
#define TSC_GROUP3_IO3 ((uint32_t)0x00000400) #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
#define TSC_GROUP3_IO4 ((uint32_t)0x00000800) #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00) #if defined(TSC_IOCCR_G5_IO1)
#define TSC_GROUP4_IO1 ((uint32_t)0x00001000) #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
#define TSC_GROUP4_IO2 ((uint32_t)0x00002000) #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
#define TSC_GROUP4_IO3 ((uint32_t)0x00004000) #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
#define TSC_GROUP4_IO4 ((uint32_t)0x00008000) #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000) #else
#define TSC_GROUP5_IO1 ((uint32_t)0x00010000) #define TSC_GROUP5_IO1 (uint32_t)(0x00000010U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */
#define TSC_GROUP5_IO2 ((uint32_t)0x00020000) #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */
#define TSC_GROUP5_IO3 ((uint32_t)0x00040000) #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */
#define TSC_GROUP5_IO4 ((uint32_t)0x00080000) #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */
#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000) #endif
#if defined(TSC_IOCCR_G6_IO1)
#define TSC_GROUP6_IO1 ((uint32_t)0x00100000) #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
#define TSC_GROUP6_IO2 ((uint32_t)0x00200000) #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
#define TSC_GROUP6_IO3 ((uint32_t)0x00400000) #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
#define TSC_GROUP6_IO4 ((uint32_t)0x00800000) #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000) #else
#define TSC_GROUP7_IO1 ((uint32_t)0x01000000) #define TSC_GROUP6_IO1 (uint32_t)(0x00000020U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */
#define TSC_GROUP7_IO2 ((uint32_t)0x02000000) #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */
#define TSC_GROUP7_IO3 ((uint32_t)0x04000000) #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */
#define TSC_GROUP7_IO4 ((uint32_t)0x08000000) #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */
#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000) #endif
#if defined(TSC_IOCCR_G7_IO1)
#define TSC_GROUP8_IO1 ((uint32_t)0x10000000) #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
#define TSC_GROUP8_IO2 ((uint32_t)0x20000000) #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
#define TSC_GROUP8_IO3 ((uint32_t)0x40000000) #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
#define TSC_GROUP8_IO4 ((uint32_t)0x80000000) #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000) #else
#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF) #define TSC_GROUP7_IO1 (uint32_t)(0x00000040U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */
#define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */
#define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */
#define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */
#endif
#if defined(TSC_IOCCR_G8_IO1)
#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
#else
#define TSC_GROUP8_IO1 (uint32_t)(0x00000080U | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */
#define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */
#define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */
#define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */
#endif
/** /**
* @} * @}
*/ */
@ -367,193 +443,201 @@ typedef struct
*/ */
/** @brief Reset TSC handle state. /** @brief Reset TSC handle state.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_TSC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
#endif
/** /**
* @brief Enable the TSC peripheral. * @brief Enable the TSC peripheral.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
/** /**
* @brief Disable the TSC peripheral. * @brief Disable the TSC peripheral.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
/** /**
* @brief Start acquisition. * @brief Start acquisition.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
/** /**
* @brief Stop acquisition. * @brief Stop acquisition.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
/** /**
* @brief Set IO default mode to output push-pull low. * @brief Set IO default mode to output push-pull low.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
/** /**
* @brief Set IO default mode to input floating. * @brief Set IO default mode to input floating.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
/** /**
* @brief Set synchronization polarity to falling edge. * @brief Set synchronization polarity to falling edge.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
/** /**
* @brief Set synchronization polarity to rising edge and high level. * @brief Set synchronization polarity to rising edge and high level.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @retval None * @retval None
*/ */
#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
/** /**
* @brief Enable TSC interrupt. * @brief Enable TSC interrupt.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __INTERRUPT__: TSC interrupt * @param __INTERRUPT__ TSC interrupt
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** /**
* @brief Disable TSC interrupt. * @brief Disable TSC interrupt.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __INTERRUPT__: TSC interrupt * @param __INTERRUPT__ TSC interrupt
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
/** @brief Check whether the specified TSC interrupt source is enabled or not. /** @brief Check whether the specified TSC interrupt source is enabled or not.
* @param __HANDLE__: TSC Handle * @param __HANDLE__ TSC Handle
* @param __INTERRUPT__: TSC interrupt * @param __INTERRUPT__ TSC interrupt
* @retval SET or RESET * @retval SET or RESET
*/ */
#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** /**
* @brief Check whether the specified TSC flag is set or not. * @brief Check whether the specified TSC flag is set or not.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __FLAG__: TSC flag * @param __FLAG__ TSC flag
* @retval SET or RESET * @retval SET or RESET
*/ */
#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** /**
* @brief Clear the TSC's pending flag. * @brief Clear the TSC's pending flag.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __FLAG__: TSC flag * @param __FLAG__ TSC flag
* @retval None * @retval None
*/ */
#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** /**
* @brief Enable schmitt trigger hysteresis on a group of IOs. * @brief Enable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
/** /**
* @brief Disable schmitt trigger hysteresis on a group of IOs. * @brief Disable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
/** /**
* @brief Open analog switch on a group of IOs. * @brief Open analog switch on a group of IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
/** /**
* @brief Close analog switch on a group of IOs. * @brief Close analog switch on a group of IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
/** /**
* @brief Enable a group of IOs in channel mode. * @brief Enable a group of IOs in channel mode.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
/** /**
* @brief Disable a group of channel IOs. * @brief Disable a group of channel IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
/** /**
* @brief Enable a group of IOs in sampling mode. * @brief Enable a group of IOs in sampling mode.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
/** /**
* @brief Disable a group of sampling IOs. * @brief Disable a group of sampling IOs.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__: IOs mask * @param __GX_IOY_MASK__ IOs mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
/** /**
* @brief Enable acquisition groups. * @brief Enable acquisition groups.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_MASK__: Groups mask * @param __GX_MASK__ Groups mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
/** /**
* @brief Disable acquisition groups. * @brief Disable acquisition groups.
* @param __HANDLE__: TSC handle * @param __HANDLE__ TSC handle
* @param __GX_MASK__: Groups mask * @param __GX_MASK__ Groups mask
* @retval None * @retval None
*/ */
#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
/** @brief Gets acquisition group status. /** @brief Gets acquisition group status.
* @param __HANDLE__: TSC Handle * @param __HANDLE__ TSC Handle
* @param __GX_INDEX__: Group index * @param __GX_INDEX__ Group index
* @retval SET or RESET * @retval SET or RESET
*/ */
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/** /**
* @} * @}
@ -565,77 +649,107 @@ typedef struct
* @{ * @{
*/ */
#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \ #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
((VAL) == TSC_CTPH_2CYCLES) || \ ((__VALUE__) == TSC_CTPH_2CYCLES) || \
((VAL) == TSC_CTPH_3CYCLES) || \ ((__VALUE__) == TSC_CTPH_3CYCLES) || \
((VAL) == TSC_CTPH_4CYCLES) || \ ((__VALUE__) == TSC_CTPH_4CYCLES) || \
((VAL) == TSC_CTPH_5CYCLES) || \ ((__VALUE__) == TSC_CTPH_5CYCLES) || \
((VAL) == TSC_CTPH_6CYCLES) || \ ((__VALUE__) == TSC_CTPH_6CYCLES) || \
((VAL) == TSC_CTPH_7CYCLES) || \ ((__VALUE__) == TSC_CTPH_7CYCLES) || \
((VAL) == TSC_CTPH_8CYCLES) || \ ((__VALUE__) == TSC_CTPH_8CYCLES) || \
((VAL) == TSC_CTPH_9CYCLES) || \ ((__VALUE__) == TSC_CTPH_9CYCLES) || \
((VAL) == TSC_CTPH_10CYCLES) || \ ((__VALUE__) == TSC_CTPH_10CYCLES) || \
((VAL) == TSC_CTPH_11CYCLES) || \ ((__VALUE__) == TSC_CTPH_11CYCLES) || \
((VAL) == TSC_CTPH_12CYCLES) || \ ((__VALUE__) == TSC_CTPH_12CYCLES) || \
((VAL) == TSC_CTPH_13CYCLES) || \ ((__VALUE__) == TSC_CTPH_13CYCLES) || \
((VAL) == TSC_CTPH_14CYCLES) || \ ((__VALUE__) == TSC_CTPH_14CYCLES) || \
((VAL) == TSC_CTPH_15CYCLES) || \ ((__VALUE__) == TSC_CTPH_15CYCLES) || \
((VAL) == TSC_CTPH_16CYCLES)) ((__VALUE__) == TSC_CTPH_16CYCLES))
#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \ #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
((VAL) == TSC_CTPL_2CYCLES) || \ ((__VALUE__) == TSC_CTPL_2CYCLES) || \
((VAL) == TSC_CTPL_3CYCLES) || \ ((__VALUE__) == TSC_CTPL_3CYCLES) || \
((VAL) == TSC_CTPL_4CYCLES) || \ ((__VALUE__) == TSC_CTPL_4CYCLES) || \
((VAL) == TSC_CTPL_5CYCLES) || \ ((__VALUE__) == TSC_CTPL_5CYCLES) || \
((VAL) == TSC_CTPL_6CYCLES) || \ ((__VALUE__) == TSC_CTPL_6CYCLES) || \
((VAL) == TSC_CTPL_7CYCLES) || \ ((__VALUE__) == TSC_CTPL_7CYCLES) || \
((VAL) == TSC_CTPL_8CYCLES) || \ ((__VALUE__) == TSC_CTPL_8CYCLES) || \
((VAL) == TSC_CTPL_9CYCLES) || \ ((__VALUE__) == TSC_CTPL_9CYCLES) || \
((VAL) == TSC_CTPL_10CYCLES) || \ ((__VALUE__) == TSC_CTPL_10CYCLES) || \
((VAL) == TSC_CTPL_11CYCLES) || \ ((__VALUE__) == TSC_CTPL_11CYCLES) || \
((VAL) == TSC_CTPL_12CYCLES) || \ ((__VALUE__) == TSC_CTPL_12CYCLES) || \
((VAL) == TSC_CTPL_13CYCLES) || \ ((__VALUE__) == TSC_CTPL_13CYCLES) || \
((VAL) == TSC_CTPL_14CYCLES) || \ ((__VALUE__) == TSC_CTPL_14CYCLES) || \
((VAL) == TSC_CTPL_15CYCLES) || \ ((__VALUE__) == TSC_CTPL_15CYCLES) || \
((VAL) == TSC_CTPL_16CYCLES)) ((__VALUE__) == TSC_CTPL_16CYCLES))
#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) #define IS_TSC_SS(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE))
#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128))) #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < 128U)))
#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2)) #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \ #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
((VAL) == TSC_PG_PRESC_DIV2) || \ ((__VALUE__) == TSC_PG_PRESC_DIV2) || \
((VAL) == TSC_PG_PRESC_DIV4) || \ ((__VALUE__) == TSC_PG_PRESC_DIV4) || \
((VAL) == TSC_PG_PRESC_DIV8) || \ ((__VALUE__) == TSC_PG_PRESC_DIV8) || \
((VAL) == TSC_PG_PRESC_DIV16) || \ ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
((VAL) == TSC_PG_PRESC_DIV32) || \ ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
((VAL) == TSC_PG_PRESC_DIV64) || \ ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((VAL) == TSC_PG_PRESC_DIV128)) ((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \ #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((VAL) == TSC_MCV_511) || \ ((__VALUE__) == TSC_MCV_511) || \
((VAL) == TSC_MCV_1023) || \ ((__VALUE__) == TSC_MCV_1023) || \
((VAL) == TSC_MCV_2047) || \ ((__VALUE__) == TSC_MCV_2047) || \
((VAL) == TSC_MCV_4095) || \ ((__VALUE__) == TSC_MCV_4095) || \
((VAL) == TSC_MCV_8191) || \ ((__VALUE__) == TSC_MCV_8191) || \
((VAL) == TSC_MCV_16383)) ((__VALUE__) == TSC_MCV_16383))
#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING)) #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO)) #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \ #define IS_TSC_MCE_IT(__VALUE__) (((__VALUE__) == DISABLE) || ((__VALUE__) == ENABLE))
((VAL) == TSC_IOMODE_CHANNEL) || \
((VAL) == TSC_IOMODE_SHIELD) || \
((VAL) == TSC_IOMODE_SAMPLING))
#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE)) #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0U) || (((__VALUE__) > 0U) && ((__VALUE__) < TSC_NB_OF_GROUPS)))
#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
#define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \
((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
(((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
(((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
(((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
(((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
(((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
(((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
(((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
(((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
(((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
(((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
(((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
(((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
(((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
(((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
(((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
(((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
(((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
(((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
(((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
(((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
(((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
(((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
(((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
(((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
(((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
(((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
(((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
(((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
(((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
(((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
(((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4)))
/** /**
* @} * @}
@ -654,6 +768,12 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

205
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart.h
View file

@ -213,19 +213,6 @@ typedef enum
Value is allowed for gState only */ Value is allowed for gState only */
} HAL_UART_StateTypeDef; } HAL_UART_StateTypeDef;
/**
* @brief HAL UART Error Code structure definition
*/
typedef enum
{
HAL_UART_ERROR_NONE = 0x00U, /*!< No error */
HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */
HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */
HAL_UART_ERROR_FE = 0x04U, /*!< frame error */
HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */
HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */
}HAL_UART_ErrorTypeDef;
/** /**
* @brief UART clock sources definition * @brief UART clock sources definition
*/ */
@ -265,17 +252,12 @@ typedef struct __UART_HandleTypeDef
uint16_t Mask; /*!< UART Rx RDR register mask */ uint16_t Mask; /*!< UART Rx RDR register mask */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
This parameter can be a value of @ref UARTEx_FIFO_mode. */
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
This parameter can be a value of @ref UARTEx_FIFO_mode. */
#endif
#if defined(USART_CR2_SLVEN)
uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used.
This parameter can be a value of @ref UARTEx_Slave_Mode. */
#endif #endif
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
@ -297,8 +279,59 @@ typedef struct __UART_HandleTypeDef
__IO uint32_t ErrorCode; /*!< UART Error code */ __IO uint32_t ErrorCode; /*!< UART Error code */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
#if defined(USART_CR1_FIFOEN)
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
#endif
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} UART_HandleTypeDef; } UART_HandleTypeDef;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL UART Callback ID enumeration definition
*/
typedef enum
{
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
#if defined(USART_CR1_FIFOEN)
HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
#endif
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
} HAL_UART_CallbackIDTypeDef;
/**
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -308,6 +341,22 @@ typedef struct __UART_HandleTypeDef
* @{ * @{
*/ */
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup UART_Stop_Bits UART Number of Stop Bits /** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{ * @{
*/ */
@ -393,6 +442,7 @@ typedef struct __UART_HandleTypeDef
#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ #define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/** /**
* @} * @}
*/ */
@ -746,7 +796,7 @@ typedef struct __UART_HandleTypeDef
*/ */
#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ #define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
@ -775,10 +825,20 @@ typedef struct __UART_HandleTypeDef
* @param __HANDLE__ UART handle. * @param __HANDLE__ UART handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0) (__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
/** @brief Flush the UART Data registers. /** @brief Flush the UART Data registers.
* @param __HANDLE__ specifies the UART Handle. * @param __HANDLE__ specifies the UART Handle.
* @retval None * @retval None
@ -787,7 +847,7 @@ typedef struct __UART_HandleTypeDef
do{ \ do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0) } while(0U)
/** @brief Clear the specified UART pending flag. /** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle. * @param __HANDLE__ specifies the UART Handle.
@ -1055,7 +1115,7 @@ typedef struct __UART_HandleTypeDef
do{ \ do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0) } while(0U)
/** @brief Disable CTS flow control. /** @brief Disable CTS flow control.
* @note This macro allows to disable CTS hardware flow control for a given UART instance, * @note This macro allows to disable CTS hardware flow control for a given UART instance,
@ -1073,7 +1133,7 @@ typedef struct __UART_HandleTypeDef
do{ \ do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0) } while(0U)
/** @brief Enable RTS flow control. /** @brief Enable RTS flow control.
* @note This macro allows to enable RTS hardware flow control for a given UART instance, * @note This macro allows to enable RTS hardware flow control for a given UART instance,
@ -1091,7 +1151,7 @@ typedef struct __UART_HandleTypeDef
do{ \ do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0) } while(0U)
/** @brief Disable RTS flow control. /** @brief Disable RTS flow control.
* @note This macro allows to disable RTS hardware flow control for a given UART instance, * @note This macro allows to disable RTS hardware flow control for a given UART instance,
@ -1109,27 +1169,33 @@ typedef struct __UART_HandleTypeDef
do{ \ do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0) } while(0U)
/** /**
* @} * @}
*/ */
/* Private variables -----------------------------------------------------*/
#if defined(USART_PRESC_PRESCALER)
/** @defgroup UART_Private_Variables UART Private Variables
* @{
*/
static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
/**
* @}
*/
#endif
/* Private macros --------------------------------------------------------*/ /* Private macros --------------------------------------------------------*/
/** @defgroup UART_Private_Macros UART Private Macros /** @defgroup UART_Private_Macros UART Private Macros
* @{ * @{
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
/** @brief Get UART clok division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval UART clock division factor
*/
#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register with LPUART. /** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock. * @param __PCLK__ LPUART clock.
@ -1137,7 +1203,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
* @param __CLOCKPRESCALER__ UART prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. /** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock. * @param __PCLK__ UART clock.
@ -1145,7 +1211,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
* @param __CLOCKPRESCALER__ UART prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. /** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock. * @param __PCLK__ UART clock.
@ -1153,8 +1219,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
* @param __CLOCKPRESCALER__ UART prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))
#else #else
/** @brief BRR division operation to set BRR register with LPUART. /** @brief BRR division operation to set BRR register with LPUART.
@ -1162,37 +1227,41 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
* @param __BAUD__ Baud rate set by the user. * @param __BAUD__ Baud rate set by the user.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. /** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock. * @param __PCLK__ UART clock.
* @param __BAUD__ Baud rate set by the user. * @param __BAUD__ Baud rate set by the user.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. /** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock. * @param __PCLK__ UART clock.
* @param __BAUD__ Baud rate set by the user. * @param __BAUD__ Baud rate set by the user.
* @retval Division result * @retval Division result
*/ */
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) #define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
#endif
#endif /* USART_PRESC_PRESCALER */
/** @brief Check whether or not UART instance is Low Power UART. /** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle. * @param __HANDLE__ specifies the UART Handle.
* @retval SET (instance is LPUART) or RESET (instance isn't LPUART) * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
*/ */
#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) #define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
/** @brief Check UART Baud rate. /** @brief Check UART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user. * @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) * The maximum Baud Rate is derived from the maximum clock on L4
* divided by the smallest oversampling used on the USART (i.e. 8) * divided by the smallest oversampling used on the USART (i.e. 8)
* (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/ */
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U)
#else
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U)
#endif
/** @brief Check UART assertion time. /** @brief Check UART assertion time.
* @param __TIME__ 5-bit value assertion time. * @param __TIME__ 5-bit value assertion time.
@ -1484,32 +1553,6 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
#endif #endif
#if defined(USART_CR1_FIFOEN)
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
#endif
/** /**
* @} * @}
*/ */
@ -1517,6 +1560,7 @@ static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 1
/* Include UART HAL Extended module */ /* Include UART HAL Extended module */
#include "stm32l4xx_hal_uart_ex.h" #include "stm32l4xx_hal_uart_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions /** @addtogroup UART_Exported_Functions UART Exported Functions
* @{ * @{
@ -1535,6 +1579,12 @@ HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1586,7 +1636,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/** /**
* @} * @}
*/ */

101
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_uart_ex.h
View file

@ -101,20 +101,19 @@ typedef struct
* @} * @}
*/ */
#if defined(USART_CR2_SLVEN) #if defined(USART_CR1_FIFOEN)
/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management /** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{ * @{
*/ */
#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ #define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ #define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/** /**
* @} * @}
*/ */
#endif
#if defined(USART_CR1_FIFOEN)
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level /** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO level * @brief UART TXFIFO threshold level
* @{ * @{
*/ */
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ #define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
@ -128,7 +127,7 @@ typedef struct
*/ */
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level /** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO level * @brief UART RXFIFO threshold level
* @{ * @{
*/ */
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ #define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
@ -167,7 +166,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
* @{ * @{
*/ */
/* IO operation functions *****************************************************/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
@ -187,14 +185,11 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
#if defined(USART_CR3_UCESM)
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
#endif /* USART_CR3_UCESM */
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
#if defined(USART_CR2_SLVEN)
HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig);
#endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
@ -202,7 +197,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint3
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
#endif #endif
/** /**
* @} * @}
*/ */
@ -211,35 +205,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup UARTEx_Private_Constants UARTEx Private Constants
* @{
*/
#if defined(USART_CR2_SLVEN)
/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode
* @{
*/
#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
/**
* @}
*/
#endif
#if defined(USART_CR1_FIFOEN)
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{ * @{
@ -250,9 +215,9 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
* @param __CLOCKSOURCE__ output variable. * @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__. * @retval UART clocking source, written in __CLOCKSOURCE__.
*/ */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) \
defined (STM32L496xx) || defined (STM32L4A6xx) || \ || defined (STM32L496xx) || defined (STM32L4A6xx) \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
if((__HANDLE__)->Instance == USART1) \ if((__HANDLE__)->Instance == USART1) \
@ -381,7 +346,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
break; \ break; \
} \ } \
} \ } \
} while(0) } while(0U)
#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) #elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
@ -469,7 +434,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
break; \ break; \
} \ } \
} \ } \
} while(0) } while(0U)
#elif defined (STM32L432xx) || defined (STM32L442xx) #elif defined (STM32L432xx) || defined (STM32L442xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
@ -536,7 +501,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
break; \ break; \
} \ } \
} \ } \
} while(0) } while(0U)
#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \ do { \
@ -645,7 +610,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
break; \ break; \
} \ } \
} \ } \
} while(0) } while(0U)
#endif #endif
/** @brief Report the UART mask to apply to retrieve the received data /** @brief Report the UART mask to apply to retrieve the received data
@ -654,7 +619,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
* by the reception API(). * by the reception API().
* This masking operation is not carried out in the case of * This masking operation is not carried out in the case of
* DMA transfers. * DMA transfers.
* @param __HANDLE__: specifies the UART Handle. * @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/ */
#define UART_MASK_COMPUTATION(__HANDLE__) \ #define UART_MASK_COMPUTATION(__HANDLE__) \
@ -663,36 +628,36 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
{ \ { \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x01FF ; \ (__HANDLE__)->Mask = 0x01FFU ; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x00FF ; \ (__HANDLE__)->Mask = 0x00FFU ; \
} \ } \
} \ } \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \ { \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x00FF ; \ (__HANDLE__)->Mask = 0x00FFU ; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x007F ; \ (__HANDLE__)->Mask = 0x007FU ; \
} \ } \
} \ } \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \ { \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x007F ; \ (__HANDLE__)->Mask = 0x007FU ; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x003F ; \ (__HANDLE__)->Mask = 0x003FU ; \
} \ } \
} \ } \
} while(0) } while(0U)
/** /**
@ -712,16 +677,6 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
#if defined(USART_CR2_SLVEN)
/**
* @brief Ensure that UART Negative Slave Select (NSS) pin management is valid.
* @param __NSS__ UART Negative Slave Select pin management.
* @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
*/
#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \
((__NSS__) == UART_NSS_SOFT))
#endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Ensure that UART TXFIFO threshold level is valid. * @brief Ensure that UART TXFIFO threshold level is valid.
@ -736,8 +691,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/** /**
* @brief Ensure that USART RXFIFO threshold level is valid. * @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ USART RXFIFO threshold level. * @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/ */
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ #define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \

199
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart.h
View file

@ -100,7 +100,6 @@ typedef struct
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
This parameter can be a value of @ref USART_ClockPrescaler. */ This parameter can be a value of @ref USART_ClockPrescaler. */
#endif #endif
} USART_InitTypeDef; } USART_InitTypeDef;
/** /**
@ -118,20 +117,6 @@ typedef enum
HAL_USART_STATE_ERROR = 0x04U /*!< Error */ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
} HAL_USART_StateTypeDef; } HAL_USART_StateTypeDef;
/**
* @brief HAL USART Error Code structure definition
*/
typedef enum
{
HAL_USART_ERROR_NONE = 0x00U, /*!< No error */
HAL_USART_ERROR_PE = 0x01U, /*!< Parity error */
HAL_USART_ERROR_NE = 0x02U, /*!< Noise error */
HAL_USART_ERROR_FE = 0x04U, /*!< frame error */
HAL_USART_ERROR_ORE = 0x08U, /*!< Overrun error */
HAL_USART_ERROR_DMA = 0x10U, /*!< DMA transfer error */
HAL_USART_ERROR_UDR = 0x20U /*!< SPI slave underrun error */
}HAL_USART_ErrorTypeDef;
/** /**
* @brief USART clock sources definitions * @brief USART clock sources definitions
*/ */
@ -173,14 +158,16 @@ typedef struct __USART_HandleTypeDef
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
This parameter can be a value of @ref USARTEx_FIFO_mode. */
#endif #endif
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
This parameter can be a value of @ref USARTEx_Slave_Mode. */ of @ref USARTEx_Slave_Mode */
#endif
#if defined(USART_CR1_FIFOEN)
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
of @ref USARTEx_FIFO_mode. */
#endif #endif
void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
@ -197,8 +184,55 @@ typedef struct __USART_HandleTypeDef
__IO uint32_t ErrorCode; /*!< USART Error code */ __IO uint32_t ErrorCode; /*!< USART Error code */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
#if defined(USART_CR1_FIFOEN)
void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */
#endif
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
} USART_HandleTypeDef; } USART_HandleTypeDef;
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL USART Callback ID enumeration definition
*/
typedef enum
{
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
#if defined(USART_CR1_FIFOEN)
HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */
#endif
HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
} HAL_USART_CallbackIDTypeDef;
/**
* @brief HAL USART Callback pointer definition
*/
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -208,6 +242,25 @@ typedef struct __USART_HandleTypeDef
* @{ * @{
*/ */
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#if defined(USART_CR2_SLVEN)
#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */
#endif
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits /** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{ * @{
*/ */
@ -300,6 +353,7 @@ typedef struct __USART_HandleTypeDef
#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ #define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ #define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ #define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/** /**
* @} * @}
*/ */
@ -324,26 +378,31 @@ typedef struct __USART_HandleTypeDef
#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ #define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */
#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ #define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */
#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ #define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
#else
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#endif #endif
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ #define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ #define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ #define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#if defined(USART_CR2_SLVEN)
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#endif
#if defined(USART_CR1_FIFOEN)
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
#else
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#endif
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#if defined(USART_CR1_FIFOEN)
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
#else
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#endif
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ #define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ #define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ #define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ #define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ #define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
#if defined(USART_CR2_SLVEN)
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#endif
/** /**
* @} * @}
*/ */
@ -360,22 +419,26 @@ typedef struct __USART_HandleTypeDef
*/ */
#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ #define USART_IT_PE 0x0028U /*!< USART parity error interruption */
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ #define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */
#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */
#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */
#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */
#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */
#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */
#endif #endif
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ #define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ #define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
#if defined(USART_CR1_FIFOEN)
#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */
#endif
#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ #define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
#define USART_IT_ERR 0x0060U /*!< USART error interruption */ #define USART_IT_ERR 0x0060U /*!< USART error interruption */
#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ #define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ #define USART_IT_NE 0x0200U /*!< USART noise error interruption */
#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ #define USART_IT_FE 0x0100U /*!< USART frame error interruption */
#if defined(USART_CR1_FIFOEN)
#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */
#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */
#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */
#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */
#endif
/** /**
* @} * @}
@ -386,16 +449,16 @@ typedef struct __USART_HandleTypeDef
*/ */
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise detected Clear Flag */ #define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#if defined(USART_CR1_FIFOEN)
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#endif
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#endif #endif
#if defined(USART_CR1_FIFOEN)
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#endif
/** /**
* @} * @}
*/ */
@ -421,7 +484,15 @@ typedef struct __USART_HandleTypeDef
* @param __HANDLE__ USART handle. * @param __HANDLE__ USART handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Check whether the specified USART flag is set or not. /** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle * @param __HANDLE__ specifies the USART Handle
@ -658,37 +729,44 @@ typedef struct __USART_HandleTypeDef
* @} * @}
*/ */
/* Private variables -----------------------------------------------------*/
#if defined(USART_PRESC_PRESCALER)
/** @defgroup USART_Private_Variables USART Private Variables
* @{
*/
static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
/**
* @}
*/
#endif
/* Private macros --------------------------------------------------------*/ /* Private macros --------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros /** @defgroup USART_Private_Macros USART Private Macros
* @{ * @{
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
/** @brief Get USART clock division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval USART clock division factor
*/
#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. /** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock. * @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user. * @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result * @retval Division result
*/ */
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#else #else
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. /** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock. * @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user. * @param __BAUD__ Baud rate set by the user.
* @retval Division result * @retval Division result
*/ */
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) #define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#endif #endif
/** @brief Check USART Baud rate. /** @brief Check USART Baud rate.
@ -696,11 +774,12 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64,
* The maximum Baud Rate is derived from the maximum clock on L4 * The maximum Baud Rate is derived from the maximum clock on L4
* divided by the smallest oversampling used on the USART (i.e. 8) * divided by the smallest oversampling used on the USART (i.e. 8)
* (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise) * (i.e. 120 MHz on STM32L4Rx/L4Sx, 80 Mhz otherwise)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 15000001U) #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U)
#else #else
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001U) #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
#endif #endif
/** /**
@ -727,7 +806,7 @@ static const uint16_t USARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64,
* @param __MODE__ USART communication mode. * @param __MODE__ USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/ */
#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00U) && ((__MODE__) != (uint32_t)0x00U)) #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/** /**
* @brief Ensure that USART oversampling is valid. * @brief Ensure that USART oversampling is valid.
@ -817,6 +896,12 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */

87
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_usart_ex.h
View file

@ -77,9 +77,30 @@
/** /**
* @} * @}
*/ */
/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
* @brief USART SLAVE mode
* @{
*/
#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
/**
* @}
*/
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
* @brief USART FIFO mode
* @{
*/
#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level /** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
* @brief USART TXFIFO level * @brief USART TXFIFO level
* @{ * @{
@ -109,35 +130,6 @@
*/ */
#endif #endif
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
#if defined(USART_CR2_SLVEN)
/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode
* @{
*/
#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
/**
* @}
*/
#endif
#if defined(USART_CR1_FIFOEN)
/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
* @{
*/
#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
#endif
/** /**
* @} * @}
*/ */
@ -148,8 +140,8 @@
*/ */
/** @brief Report the USART clock source. /** @brief Report the USART clock source.
* @param __HANDLE__: specifies the USART Handle. * @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__: output variable. * @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__. * @retval the USART clocking source, written in __CLOCKSOURCE__.
*/ */
#if defined (STM32L432xx) || defined (STM32L442xx) #if defined (STM32L432xx) || defined (STM32L442xx)
@ -282,36 +274,36 @@
{ \ { \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x01FF ; \ (__HANDLE__)->Mask = 0x01FFU; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x00FF ; \ (__HANDLE__)->Mask = 0x00FFU; \
} \ } \
} \ } \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \ { \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x00FF ; \ (__HANDLE__)->Mask = 0x00FFU; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x007F ; \ (__HANDLE__)->Mask = 0x007FU; \
} \ } \
} \ } \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \ { \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \ { \
(__HANDLE__)->Mask = 0x007F ; \ (__HANDLE__)->Mask = 0x007FU; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Mask = 0x003F ; \ (__HANDLE__)->Mask = 0x003FU; \
} \ } \
} \ } \
} while(0) } while(0U)
/** /**
@ -322,6 +314,7 @@
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ #define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \ ((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B)) ((__LENGTH__) == USART_WORDLENGTH_9B))
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
/** /**
* @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
@ -330,9 +323,25 @@
*/ */
#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ #define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
((__NSS__) == USART_NSS_SOFT)) ((__NSS__) == USART_NSS_SOFT))
/**
* @brief Ensure that USART Slave Mode is valid.
* @param __STATE__ USART Slave Mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
((__STATE__) == USART_SLAVEMODE_ENABLE))
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/**
* @brief Ensure that USART FIFO mode is valid.
* @param __STATE__ USART FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
((__STATE__) == USART_FIFOMODE_ENABLE))
/** /**
* @brief Ensure that USART TXFIFO threshold level is valid. * @brief Ensure that USART TXFIFO threshold level is valid.
* @param __THRESHOLD__ USART TXFIFO threshold level. * @param __THRESHOLD__ USART TXFIFO threshold level.
@ -357,7 +366,6 @@
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
#endif #endif
/** /**
* @} * @}
*/ */
@ -391,7 +399,6 @@ HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);

32
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_hal_wwdg.h
View file

@ -80,13 +80,35 @@ typedef struct
/** /**
* @brief WWDG handle Structure definition * @brief WWDG handle Structure definition
*/ */
typedef struct typedef struct __WWDG_HandleTypeDef
{ {
WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif
} WWDG_HandleTypeDef; } WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL WWDG common Callback ID enumeration definition
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
}HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
#endif
/** /**
* @} * @}
*/ */
@ -120,7 +142,7 @@ typedef struct
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ #define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/** /**
* @} * @}
*/ */
@ -247,6 +269,12 @@ typedef struct
/* Initialization/de-initialization functions **********************************/ /* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif
/** /**
* @} * @}
*/ */

142
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_adc.h
View file

@ -368,9 +368,13 @@ extern "C" {
#define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ #define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */ /* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#else
#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#endif
#define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ #define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
@ -2130,7 +2134,7 @@ typedef struct
* @brief Helper macro to convert the ADC conversion data from * @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution. * a resolution to another resolution.
* @param __DATA__ ADC conversion data to be converted * @param __DATA__ ADC conversion data to be converted
* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_10B
@ -2404,6 +2408,9 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis
#else #else
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{ {
/* Prevent unused argument(s) compilation warning */
(void)(Register);
/* Retrieve address of register DR */ /* Retrieve address of register DR */
return (uint32_t)&(ADCx->DR); return (uint32_t)&(ADCx->DR);
} }
@ -2501,12 +2508,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
* For ADC conversion of internal channels, * For ADC conversion of internal channels,
* a sampling time minimum value is required. * a sampling time minimum value is required.
* Refer to device datasheet. * Refer to device datasheet.
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
* CCR TSEN LL_ADC_SetCommonPathInternalCh\n * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
* CCR VBATEN LL_ADC_SetCommonPathInternalCh * CCR VBATEN LL_ADC_SetCommonPathInternalCh
@ -3193,7 +3194,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
/** /**
* @brief Get ADC group regular conversion trigger source internal (SW start) * @brief Get ADC group regular conversion trigger source internal (SW start)
or external. * or external.
* @note In case of group regular trigger source set to external trigger, * @note In case of group regular trigger source set to external trigger,
* to determine which peripheral is selected as external trigger, * to determine which peripheral is selected as external trigger,
* use function @ref LL_ADC_REG_GetTriggerSource(). * use function @ref LL_ADC_REG_GetTriggerSource().
@ -3204,7 +3205,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)); return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
} }
/** /**
@ -3938,7 +3939,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)); return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
} }
/** /**
@ -4552,6 +4553,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
/* because containing other bits reserved for other purpose. */ /* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */ /* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */ /* "ExternalTriggerEdge" is discarded. */
register uint32_t is_trigger_not_sw = (uint32_t)(TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE);
MODIFY_REG(ADCx->JSQR , MODIFY_REG(ADCx->JSQR ,
ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN | ADC_JSQR_JEXTEN |
@ -4561,7 +4563,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ1 |
ADC_JSQR_JL , ADC_JSQR_JL ,
TriggerSource | TriggerSource |
(ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) | (ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
@ -4815,7 +4817,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32
* not available in differential mode. * not available in differential mode.
* @note When configuring a channel 'i' in differential mode, * @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately. * the channel 'i+1' is not usable separately.
* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
* are internally fixed to single-ended inputs configuration. * are internally fixed to single-ended inputs configuration.
* @note For ADC channels configured in differential mode, both inputs * @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV. * should be biased at (Vref+)/2 +/-200mV.
@ -4825,7 +4827,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32
* ADC must be ADC disabled. * ADC must be ADC disabled.
* @note One or several values can be selected. * @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
* @param ADCx ADC instance * @param ADCx ADC instance
* @param Channel This parameter can be one of the following values: * @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_1
@ -4842,6 +4844,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32
* @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @param SingleDiff This parameter can be a combination of the following values: * @param SingleDiff This parameter can be a combination of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
@ -4872,12 +4875,12 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha
* not available in differential mode. * not available in differential mode.
* @note When configuring a channel 'i' in differential mode, * @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately. * the channel 'i+1' is not usable separately.
* @note On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available) * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
* are internally fixed to single-ended inputs configuration. * are internally fixed to single-ended inputs configuration.
* @note One or several values can be selected. In this case, the value * @note One or several values can be selected. In this case, the value
* returned is null if all channels are in single ended-mode. * returned is null if all channels are in single ended-mode.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
* @param ADCx ADC instance * @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values: * @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_1
@ -4894,6 +4897,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha
* @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @retval 0: channel in single-ended mode, else: channel in differential mode * @retval 0: channel in single-ended mode, else: channel in differential mode
*/ */
__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
@ -5936,7 +5940,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));
} }
/** /**
@ -5985,7 +5989,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));
} }
/** /**
@ -6045,7 +6049,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
} }
/** /**
@ -6056,7 +6060,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
} }
/** /**
@ -6100,7 +6104,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleD
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
} }
/** /**
@ -6167,7 +6171,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
} }
/** /**
@ -6178,7 +6182,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
} }
/** /**
@ -6350,7 +6354,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
} }
/** /**
@ -6361,7 +6365,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)); return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
} }
/** /**
@ -6537,7 +6541,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
} }
/** /**
@ -6548,7 +6552,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); return (uint32_t)(READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
} }
/** /**
@ -6559,7 +6563,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
} }
/** /**
@ -6570,7 +6574,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
} }
/** /**
@ -6581,7 +6585,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
} }
/** /**
@ -6592,7 +6596,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
} }
/** /**
@ -6603,7 +6607,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
} }
/** /**
@ -6614,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
} }
/** /**
@ -6625,7 +6629,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
} }
/** /**
@ -6636,7 +6640,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
} }
/** /**
@ -6647,7 +6651,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)); return (uint32_t)(READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
} }
/** /**
@ -6784,7 +6788,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
} }
/** /**
@ -6796,7 +6800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
} }
/** /**
@ -6808,7 +6812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
} }
/** /**
@ -6820,7 +6824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
} }
/** /**
@ -6832,7 +6836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
} }
/** /**
@ -6844,7 +6848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
} }
/** /**
@ -6856,7 +6860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
} }
/** /**
@ -6868,7 +6872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
} }
/** /**
@ -6880,7 +6884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
} }
/** /**
@ -6892,7 +6896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
} }
/** /**
@ -6904,7 +6908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
} }
/** /**
@ -6916,7 +6920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
} }
/** /**
@ -6928,7 +6932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
} }
/** /**
@ -6940,7 +6944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
} }
/** /**
@ -6952,7 +6956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
} }
/** /**
@ -6964,7 +6968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
} }
/** /**
@ -6976,7 +6980,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
} }
/** /**
@ -6988,7 +6992,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
} }
/** /**
@ -7000,7 +7004,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
} }
/** /**
@ -7012,7 +7016,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
} }
/** /**
@ -7024,7 +7028,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
} }
/** /**
@ -7036,7 +7040,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{ {
return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)); return (uint32_t)(READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
} }
#endif /* ADC_MULTIMODE_SUPPORT */ #endif /* ADC_MULTIMODE_SUPPORT */
@ -7299,7 +7303,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
} }
/** /**
@ -7311,7 +7315,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
} }
/** /**
@ -7323,7 +7327,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
} }
/** /**
@ -7335,7 +7339,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
} }
/** /**
@ -7347,7 +7351,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
} }
/** /**
@ -7359,7 +7363,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
} }
/** /**
@ -7371,7 +7375,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
} }
/** /**
@ -7383,7 +7387,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
} }
/** /**
@ -7395,7 +7399,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
} }
/** /**
@ -7407,7 +7411,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
} }
/** /**
@ -7419,7 +7423,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
*/ */
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
{ {
return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)); return (uint32_t)(READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
} }
/** /**

4
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_comp.h
View file

@ -875,6 +875,10 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
* @} * @}
*/ */
/**
* @}
*/
#endif /* COMP1 || COMP2 */ #endif /* COMP1 || COMP2 */
/** /**

21
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_crc.h
View file

@ -134,7 +134,7 @@ extern "C" {
* @param __VALUE__ Value to be written in the register * @param __VALUE__ Value to be written in the register
* @retval None * @retval None
*/ */
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/** /**
* @brief Read a value in CRC register * @brief Read a value in CRC register
@ -352,7 +352,10 @@ __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
*/ */
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{ {
*(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData; __IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);
*pReg = InData;
} }
/** /**
@ -416,10 +419,11 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
/** /**
* @brief Return data stored in the Independent Data(IDR) register. * @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte. * @note This register can be used as a temporary storage location.
* @note Refer to the Reference Manual to get the authorized data length in bits.
* @rmtoll IDR IDR LL_CRC_Read_IDR * @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance * @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). * @retval Value stored in CRC_IDR register
*/ */
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{ {
@ -428,15 +432,20 @@ __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
/** /**
* @brief Store data in the Independent Data(IDR) register. * @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte. * @note This register can be used as a temporary storage location.
* @note Refer to the Reference Manual to get the authorized data length in bits.
* @rmtoll IDR IDR LL_CRC_Write_IDR * @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance * @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF * @param InData value to be stored in CRC_IDR register
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{ {
#if (CRC_IDR_IDR == 0x0FFU)
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
#else
WRITE_REG(CRCx->IDR, InData);
#endif
} }
/** /**
* @} * @}

4
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dac.h
View file

@ -861,7 +861,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
} }
/** /**
* @brief Set the noise waveform generation for the selected DAC channel: * @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register). * Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
@ -933,7 +933,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
} }
/** /**
* @brief Set the triangle waveform generation for the selected DAC channel: * @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude. * triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude

57
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_dma2d.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_LL_DMA2D_H #ifndef STM32L4xx_LL_DMA2D_H
#define __STM32L4xx_LL_DMA2D_H #define STM32L4xx_LL_DMA2D_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -148,7 +148,8 @@ typedef struct
#endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
uint32_t LineOffset; /*!< Specifies the output line offset value. uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on STM32L496xx/STM32L4A6xx - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF on devices
where the Line Offset Mode feature is available.
else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices. else between Min_Data = 0x0000 and Max_Data = 0xFFFF on other devices.
This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
@ -271,6 +272,7 @@ typedef struct
- @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
} LL_DMA2D_LayerCfgTypeDef; } LL_DMA2D_LayerCfgTypeDef;
/** /**
@ -422,7 +424,7 @@ typedef struct
/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
* @{ * @{
*/ */
#define LL_DMA2D_SWAP_MODE_REGULAR ((uint32_t)0x00000000) /*!< Regular order */ #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
/** /**
* @} * @}
@ -447,11 +449,12 @@ typedef struct
* @} * @}
*/ */
#if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
* @{ * @{
*/ */
#define LL_DMA2D_LINE_OFFSET_PIXELS ((uint32_t)0x00000000) /*!< Line offsets are expressed in pixels */ #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
/** /**
* @} * @}
@ -467,6 +470,7 @@ typedef struct
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@ -487,7 +491,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register * @param __VALUE__ Value to be written in the register
* @retval None * @retval None
*/ */
#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/** /**
* @brief Read a value in DMA2D register. * @brief Read a value in DMA2D register.
@ -495,7 +499,7 @@ typedef struct
* @param __REG__ Register to be read * @param __REG__ Register to be read
* @retval Register value * @retval Register value
*/ */
#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/** /**
* @} * @}
*/ */
@ -532,7 +536,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
} }
/** /**
@ -569,7 +573,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
} }
/** /**
@ -594,7 +598,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
} }
/** /**
@ -723,6 +727,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
} }
#if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
/** /**
* @brief Set DMA2D output swap mode. * @brief Set DMA2D output swap mode.
@ -995,7 +1000,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)); return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
} }
/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
@ -1044,7 +1049,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)); return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
} }
/** /**
@ -1430,7 +1435,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)); return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
} }
/** /**
@ -1787,7 +1792,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
} }
/** /**
@ -1798,7 +1803,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
} }
/** /**
@ -1809,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
} }
/** /**
@ -1820,7 +1825,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
} }
/** /**
@ -1831,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
} }
/** /**
@ -1842,7 +1847,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)); return (uint32_t)(READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
} }
/** /**
@ -2059,7 +2064,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
} }
/** /**
@ -2070,7 +2075,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
} }
/** /**
@ -2081,7 +2086,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
} }
/** /**
@ -2092,7 +2097,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
} }
/** /**
@ -2103,7 +2108,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
} }
/** /**
@ -2114,7 +2119,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
*/ */
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
{ {
return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)); return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
} }
@ -2163,6 +2168,6 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
} }
#endif #endif
#endif /* __STM32L4xx_LL_DMA2D_H */ #endif /* STM32L4xx_LL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

505
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_fmc.h
View file

@ -48,8 +48,6 @@ extern "C" {
* @{ * @{
*/ */
#if defined(FMC_BANK1)
/** @addtogroup FMC_LL /** @addtogroup FMC_LL
* @{ * @{
*/ */
@ -57,215 +55,94 @@ extern "C" {
/** @addtogroup FMC_LL_Private_Macros /** @addtogroup FMC_LL_Private_Macros
* @{ * @{
*/ */
#if defined(FMC_BANK1)
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
((__BANK__) == FMC_NORSRAM_BANK2) || \ ((__BANK__) == FMC_NORSRAM_BANK2) || \
((__BANK__) == FMC_NORSRAM_BANK3) || \ ((__BANK__) == FMC_NORSRAM_BANK3) || \
((__BANK__) == FMC_NORSRAM_BANK4)) ((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM) || \ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \ ((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \ ((__SIZE__) == FMC_PAGE_SIZE_256) || \
((__SIZE__) == FMC_PAGE_SIZE_512) || \ ((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024)) ((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#if defined(FMC_BCR1_WFDIS) #if defined(FMC_BCR1_WFDIS)
#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#endif /* FMC_BCR1_WFDIS */ #endif /* FMC_BCR1_WFDIS */
#if defined(FMC_BCRx_NBLSET)
#define IS_FMC_NBLSETUP_TIME(__TIME__) ((__TIME__) <= 3)
#endif /* FMC_BCRx_NBLSET */
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \ ((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \ ((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D)) ((__MODE__) == FMC_ACCESS_MODE_D))
#if defined(FMC_BCRx_NBLSET)
#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
((__NBL__) == FMC_NBL_SETUPTIME_1) || \
((__NBL__) == FMC_NBL_SETUPTIME_2) || \
((__NBL__) == FMC_NBL_SETUPTIME_3))
#endif /* FMC_BCRx_NBLSET */
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
#if defined(FMC_BTRx_DATAHLD)
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3)
#endif /* FMC_BTRx_DATAHLD */
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE)) ((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
* @{
*/
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
* @{
*/
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
/** #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254)
* @} #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254)
*/ #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254)
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254)
/** @defgroup FMC_Setup_Time FMC_Setup_Time
* @{
*/
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
* @{
*/
#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
* @{
*/
#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
* @{
*/
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
* @{
*/
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
* @{
*/
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
/**
* @}
*/
/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
* @{
*/
#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
/**
* @}
*/
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ #endif /* FMC_BANK3 */
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
/** @defgroup FMC_Data_Latency FMC Data Latency
* @{
*/
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
/**
* @}
*/
/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
* @{
*/
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
/**
* @}
*/
/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
* @{
*/
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
/**
* @}
*/
/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
* @{
*/
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
/**
* @}
*/
#if defined(FMC_BTRx_DATAHLD)
/** @defgroup FMC_Data_Hold_Time
* @{
*/
#define IS_FMC_DATAHOLD_TIME(__TIME__) ((__TIME__) <= 3)
/**
* @}
*/
#endif /* FMC_BTRx_DATAHLD */
/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
* @{
*/
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
/**
* @}
*/
/** /**
* @} * @}
@ -273,20 +150,29 @@ extern "C" {
/* Exported typedef ----------------------------------------------------------*/ /* Exported typedef ----------------------------------------------------------*/
/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
* @{ * @{
*/ */
#if defined(FMC_BANK1)
#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_TypeDef FMC_Bank3_TypeDef #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
#endif /* FMC_BANK3 */
#if defined(FMC_BANK1)
#define FMC_NORSRAM_DEVICE FMC_Bank1_R #define FMC_NORSRAM_DEVICE FMC_Bank1_R
#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_DEVICE FMC_Bank3_R #define FMC_NAND_DEVICE FMC_Bank3_R
#endif /* FMC_BANK3 */
#if defined(FMC_BANK1)
/** /**
* @brief FMC_NORSRAM Configuration Structure definition * @brief FMC NORSRAM Configuration Structure definition
*/ */
typedef struct typedef struct
{ {
@ -345,19 +231,18 @@ typedef struct
This parameter can be a value of @ref FMC_Write_FIFO. This parameter can be a value of @ref FMC_Write_FIFO.
@note This Parameter is not available for STM32L47x/L48x devices. */ @note This Parameter is not available for STM32L47x/L48x devices. */
#if defined(FMC_BCRx_NBLSET)
uint32_t NBLSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the byte lane (NBL) setup time from NBLx low to Chip select NEx low.
This parameter can be a value between Min_Data = 0 and Max_Data = 3.
@note This parameter is used for SRAMs, ROMs and NOR Flash memories. */
#endif /* FMC_BCRx_NBLSET */
uint32_t PageSize; /*!< Specifies the memory page size. uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FMC_Page_Size */ This parameter can be a value of @ref FMC_Page_Size */
#if defined(FMC_BCRx_NBLSET)
uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
This parameter can be a value of @ref FMC_Byte_Lane */
#endif /* FMC_BCRx_NBLSET */
}FMC_NORSRAM_InitTypeDef; }FMC_NORSRAM_InitTypeDef;
/** /**
* @brief FMC_NORSRAM Timing parameters structure definition * @brief FMC NORSRAM Timing parameters structure definition
*/ */
typedef struct typedef struct
{ {
@ -381,10 +266,7 @@ typedef struct
uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data hold time. the duration of the data hold time.
This parameter can be a value between Min_Data = 0 and Max_Data = 3. This parameter can be a value between Min_Data = 0 and Max_Data = 3.
@note This parameter value corresponds to x HCLK cycles for read and @note This parameter is used for used in asynchronous accesses. */
x+1 HCLK cycles for write.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
#endif /* FMC_BTRx_DATAHLD */ #endif /* FMC_BTRx_DATAHLD */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
@ -407,11 +289,12 @@ typedef struct
uint32_t AccessMode; /*!< Specifies the asynchronous access mode. uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */ This parameter can be a value of @ref FMC_Access_Mode */
}FMC_NORSRAM_TimingTypeDef; }FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** /**
* @brief FMC_NAND Configuration Structure definition * @brief FMC NAND Configuration Structure definition
*/ */
typedef struct typedef struct
{ {
@ -437,11 +320,10 @@ typedef struct
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low. delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FMC_NAND_InitTypeDef; }FMC_NAND_InitTypeDef;
/** /**
* @brief FMC_NAND Timing parameters structure definition * @brief FMC NAND Timing parameters structure definition
*/ */
typedef struct typedef struct
{ {
@ -449,51 +331,50 @@ typedef struct
the command assertion for NAND-Flash read or write access the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on to common/Attribute or I/O memory space (depending on
the memory space timing to be configured). the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the common/Attribute or I/O memory space (depending on the
memory space timing to be configured). memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion (and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing or I/O memory space (depending on the memory space timing
to be configured). to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured). on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
}FMC_NAND_PCC_TimingTypeDef; }FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
* @{ * @{
*/ */
#if defined(FMC_BANK1)
/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
* @{ * @{
*/ */
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{ * @{
*/ */
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
/** /**
* @} * @}
*/ */
@ -501,10 +382,8 @@ typedef struct
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{ * @{
*/ */
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN) #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
/** /**
* @} * @}
*/ */
@ -512,11 +391,9 @@ typedef struct
/** @defgroup FMC_Memory_Type FMC Memory Type /** @defgroup FMC_Memory_Type FMC Memory Type
* @{ * @{
*/ */
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0) #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
#define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1) #define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
/** /**
* @} * @}
*/ */
@ -524,11 +401,9 @@ typedef struct
/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
* @{ * @{
*/ */
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0) #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1) #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
/** /**
* @} * @}
*/ */
@ -536,9 +411,8 @@ typedef struct
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{ * @{
*/ */
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN) #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
/** /**
* @} * @}
*/ */
@ -546,26 +420,17 @@ typedef struct
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{ * @{
*/ */
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN) #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
/** /**
* @} * @}
*/ */
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{ * @{
*/ */
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL) #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -573,10 +438,8 @@ typedef struct
/** @defgroup FMC_Wait_Timing FMC Wait Timing /** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{ * @{
*/ */
#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG) #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
/** /**
* @} * @}
*/ */
@ -584,10 +447,8 @@ typedef struct
/** @defgroup FMC_Write_Operation FMC Write Operation /** @defgroup FMC_Write_Operation FMC Write Operation
* @{ * @{
*/ */
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN) #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
/** /**
* @} * @}
*/ */
@ -595,10 +456,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal FMC Wait Signal /** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{ * @{
*/ */
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN) #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
/** /**
* @} * @}
*/ */
@ -606,10 +465,8 @@ typedef struct
/** @defgroup FMC_Extended_Mode FMC Extended Mode /** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{ * @{
*/ */
#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD) #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
/** /**
* @} * @}
*/ */
@ -617,10 +474,8 @@ typedef struct
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{ * @{
*/ */
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT) #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
/** /**
* @} * @}
*/ */
@ -628,7 +483,7 @@ typedef struct
/** @defgroup FMC_Page_Size FMC Page Size /** @defgroup FMC_Page_Size FMC Page Size
* @{ * @{
*/ */
#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
@ -640,18 +495,16 @@ typedef struct
/** @defgroup FMC_Write_Burst FMC Write Burst /** @defgroup FMC_Write_Burst FMC Write Burst
* @{ * @{
*/ */
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
#define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW) #define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
/** /**
* @} * @}
*/ */
/** @defgroup FMC_Continous_Clock FMC Continous Clock /** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{ * @{
*/ */
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN) #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
/** /**
* @} * @}
@ -662,17 +515,16 @@ typedef struct
* @{ * @{
*/ */
#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
/** /**
* @} * @}
*/ */
#endif /* FMC_BCR1_WFDIS */ #endif /* FMC_BCR1_WFDIS */
/** @defgroup FMC_Access_Mode FMC Access Mode /** @defgroup FMC_Access_Mode FMC Access Mode
* @{ * @{
*/ */
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0) #define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1) #define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1)) #define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
@ -680,20 +532,33 @@ typedef struct
/** /**
* @} * @}
*/ */
#if defined(FMC_BCRx_NBLSET)
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
* @{
*/
#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U)
#define FMC_NBL_SETUPTIME_1 ((uint32_t)FMC_BCRx_NBLSET_0)
#define FMC_NBL_SETUPTIME_2 ((uint32_t)FMC_BCRx_NBLSET_1)
#define FMC_NBL_SETUPTIME_3 ((uint32_t)(FMC_BCRx_NBLSET_0 | FMC_BCRx_NBLSET_1))
/**
* @}
*/
#endif /* FMC_BCRx_NBLSET */
/** /**
* @} * @}
*/ */
#endif /* FMC_BANK1 */
/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller #if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
* @{ * @{
*/ */
/** @defgroup FMC_NAND_Bank FMC NAND Bank /** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{ * @{
*/ */
#define FMC_NAND_BANK3 ((uint32_t)0x00000100) #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
/** /**
* @} * @}
*/ */
@ -701,9 +566,8 @@ typedef struct
/** @defgroup FMC_Wait_feature FMC Wait feature /** @defgroup FMC_Wait_feature FMC Wait feature
* @{ * @{
*/ */
#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN) #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCR_PWAITEN)
/** /**
* @} * @}
*/ */
@ -719,19 +583,17 @@ typedef struct
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{ * @{
*/ */
#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0) #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCR_PWID_0)
/** /**
* @} * @}
*/ */
/** @defgroup FMC_ECC FMC NAND ECC /** @defgroup FMC_ECC FMC ECC
* @{ * @{
*/ */
#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN) #define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCR_ECCEN)
/** /**
* @} * @}
*/ */
@ -739,38 +601,46 @@ typedef struct
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{ * @{
*/ */
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0) #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCR_ECCPS_0)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCR_ECCPS_1)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1) #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_1)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2) #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCR_ECCPS_2)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2) #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCR_ECCPS_0|FMC_PCR_ECCPS_2)
/** /**
* @} * @}
*/ */
/** @defgroup FMC_Interrupt_definition FMC Interrupt definition /**
* @brief FMC Interrupt definition * @}
*/
#endif /* FMC_BANK3 */
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{ * @{
*/ */
#if defined(FMC_BANK3)
#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN) #define FMC_IT_RISING_EDGE ((uint32_t)FMC_SR_IREN)
#define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN) #define FMC_IT_LEVEL ((uint32_t)FMC_SR_ILEN)
#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN) #define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SR_IFEN)
#endif /* FMC_BANK3 */
/** /**
* @} * @}
*/ */
/** @defgroup FMC_Flag_definition FMC Flag definition /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @brief FMC Flag definition
* @{ * @{
*/ */
#if defined(FMC_BANK3)
#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS) #define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SR_IRS)
#define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS) #define FMC_FLAG_LEVEL ((uint32_t)FMC_SR_ILS)
#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS) #define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SR_IFS)
#define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT) #define FMC_FLAG_FEMPT ((uint32_t)FMC_SR_FEMPT)
#endif /* FMC_BANK3 */
/**
* @}
*/
/** /**
* @} * @}
*/ */
@ -779,17 +649,13 @@ typedef struct
* @} * @}
*/ */
/** /* Private macro -------------------------------------------------------------*/
* @} /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
* @{ * @{
*/ */
/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros #if defined(FMC_BANK1)
/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations * @brief macros to handle NOR device enable/disable and read/write operations
* @{ * @{
*/ */
@ -798,23 +664,25 @@ typedef struct
* @brief Enable the NORSRAM device access. * @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance * @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank * @param __BANK__ FMC_NORSRAM Bank
* @retval none * @retval None
*/ */
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
/** /**
* @brief Disable the NORSRAM device access. * @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance * @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank * @param __BANK__ FMC_NORSRAM Bank
* @retval none * @retval None
*/ */
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN) #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
/** /**
* @} * @}
*/ */
#endif /* FMC_BANK1 */
/** @defgroup FMC_NAND_Macros FMC NAND Macros #if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable * @brief macros to handle NAND device enable/disable
* @{ * @{
*/ */
@ -822,32 +690,29 @@ typedef struct
/** /**
* @brief Enable the NAND device access. * @brief Enable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance * @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None * @retval None
*/ */
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
/** /**
* @brief Disable the NAND device access. * @brief Disable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance * @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None * @retval None
*/ */
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
/** /**
* @} * @}
*/ */
/** @defgroup FMC_Interrupt FMC Interrupt /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
* @brief macros to handle FMC interrupts * @brief macros to handle NAND interrupts
* @{ * @{
*/ */
/** /**
* @brief Enable the NAND device interrupt. * @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND Instance * @param __INSTANCE__ FMC_NAND instance
* @param __BANK__ FMC_NAND Bank
* @param __INTERRUPT__ FMC_NAND interrupt * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE Interrupt rising edge. * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
@ -855,12 +720,11 @@ typedef struct
* @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None * @retval None
*/ */
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
/** /**
* @brief Disable the NAND device interrupt. * @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND Instance * @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __INTERRUPT__ FMC_NAND interrupt * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE Interrupt rising edge. * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
@ -868,7 +732,7 @@ typedef struct
* @arg FMC_IT_FALLING_EDGE Interrupt falling edge. * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None * @retval None
*/ */
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR, (__INTERRUPT__)) #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
/** /**
* @brief Get flag status of the NAND device. * @brief Get flag status of the NAND device.
@ -887,7 +751,6 @@ typedef struct
/** /**
* @brief Clear flag status of the NAND device. * @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance * @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __FLAG__ FMC_NAND flag * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag. * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
@ -896,85 +759,84 @@ typedef struct
* @arg FMC_FLAG_FEMPT FIFO empty flag. * @arg FMC_FLAG_FEMPT FIFO empty flag.
* @retval None * @retval None
*/ */
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR, (__FLAG__)) #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
/**
* @}
*/
#endif /* FMC_BANK3 */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
/** @addtogroup FMC_LL_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup FMC_NORSRAM #if defined(FMC_BANK1)
/** @defgroup FMC_LL_NORSRAM NOR SRAM
* @{ * @{
*/ */
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
/** @addtogroup FMC_NORSRAM_Group1
* @{ * @{
*/ */
/* FMC_NORSRAM Controller functions ******************************************/
/* Initialization/de-initialization functions */
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/** /**
* @} * @}
*/ */
/** @addtogroup FMC_NORSRAM_Group2 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{ * @{
*/ */
/* FMC_NORSRAM Control functions */
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* FMC_BANK1 */
/** @addtogroup FMC_NAND #if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND NAND
* @{ * @{
*/ */
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
/* FMC_NAND Controller functions **********************************************/
/* Initialization/de-initialization functions */
/** @addtogroup FMC_NAND_Exported_Functions_Group1
* @{ * @{
*/ */
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/** /**
* @} * @}
*/ */
/* FMC_NAND Control functions */ /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
/** @addtogroup FMC_NAND_Exported_Functions_Group2
* @{ * @{
*/ */
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
/** /**
* @} * @}
@ -984,16 +846,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u
* @} * @}
*/ */
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
/** /**
* @} * @}
*/ */
@ -1005,4 +857,3 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u
#endif /* __STM32L4xx_LL_FMC_H */ #endif /* __STM32L4xx_LL_FMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

4
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_i2c.h
View file

@ -594,7 +594,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
*/ */
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{ {
register uint32_t data_reg_addr = 0U; register uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{ {
@ -2108,7 +2108,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
{ {
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request); SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
} }
/** /**

2
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lptim.h
View file

@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
} }
/** /**
* @brief Inform application whether a autoreload match interrupt has occured. * @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance * @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).

71
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_lpuart.h
View file

@ -169,7 +169,7 @@ typedef struct
*/ */
#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
#define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */
#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
@ -488,15 +488,14 @@ typedef struct
* @arg @ref LL_LPUART_PRESCALER_DIV64 * @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256 * @arg @ref LL_LPUART_PRESCALER_DIV256
* @param __PRESCALER__ Prescaler value
@endif @endif
* @param __BAUDRATE__ Baud Rate value to achieve * @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling * @retval LPUARTDIV value to be used for BRR register filling
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#else #else
#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK) #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#endif #endif
/** /**
@ -725,6 +724,43 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
} }
#if defined(USART_CR3_UCESM)
/**
* @brief LPUART Clock enabled in STOP Mode
* @note When this function is called, LPUART Clock is enabled while in STOP mode
* @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief LPUART clock disabled in STOP Mode
* @note When this function is called, LPUART Clock is disabled while in STOP mode
* @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief Indicate if LPUART clock is enabled in STOP Mode
* @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx)
{
return (READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
}
#endif /* USART_CR3_UCESM */
/** /**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
@ -948,7 +984,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
*/ */
__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
} }
/** /**
@ -1409,7 +1445,7 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri
#endif #endif
{ {
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, (uint16_t)PrescalerValue, BaudRate);
#else #else
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
#endif #endif
@ -1448,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t
register uint32_t lpuartdiv = 0x0U; register uint32_t lpuartdiv = 0x0U;
register uint32_t brrresult = 0x0U; register uint32_t brrresult = 0x0U;
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue])); register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
#endif #endif
lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
@ -1684,7 +1720,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
@ -1724,7 +1759,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
@ -1852,7 +1886,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if the LPUART TX FIFO Empty Flag is set or not * @brief Check if the LPUART TX FIFO Empty Flag is set or not
* @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
@ -1922,13 +1955,13 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
/** /**
* @brief Clear Noise detected Flag * @brief Clear Noise detected Flag
* @rmtoll ICR NCF LL_LPUART_ClearFlag_NE * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
* @param LPUARTx LPUART Instance * @param LPUARTx LPUART Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
{ {
WRITE_REG(LPUARTx->ICR, USART_ICR_NCF); WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
} }
/** /**
@ -1954,7 +1987,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Clear TX FIFO Empty Flag * @brief Clear TX FIFO Empty Flag
* @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE
@ -2031,7 +2063,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
@ -2071,7 +2102,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
@ -2122,7 +2152,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Enable TX FIFO Empty Interrupt * @brief Enable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
@ -2184,7 +2213,6 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Enable TX FIFO Threshold Interrupt * @brief Enable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
@ -2220,7 +2248,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
@ -2260,7 +2287,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
@ -2311,7 +2337,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Disable TX FIFO Empty Interrupt * @brief Disable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
@ -2373,7 +2398,6 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Disable TX FIFO Threshold Interrupt * @brief Disable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
@ -2409,7 +2433,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
@ -2449,7 +2472,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
@ -2498,8 +2520,8 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
{ {
return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
} }
#if defined(USART_CR1_FIFOEN)
#if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
* @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
@ -2557,7 +2579,6 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
* @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT

61
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rcc.h
View file

@ -153,6 +153,14 @@ typedef struct
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */ #endif /* HSI48_VALUE */
#endif /* RCC_HSI48_SUPPORT */ #endif /* RCC_HSI48_SUPPORT */
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/** /**
* @} * @}
*/ */
@ -2080,6 +2088,16 @@ __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
} }
/**
* @brief Check if HSI is enabled in stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
{
return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
}
/** /**
* @brief Enable HSI oscillator * @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable * @rmtoll CR HSION LL_RCC_HSI_Enable
@ -3850,6 +3868,35 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM,
Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
} }
/**
* @brief Configure PLL clock source
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
* @param PLLSource This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_MSI
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
}
/**
* @brief Get the oscillator used as PLL clock source.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_MSI
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
}
/** /**
* @brief Get Main PLL multiplication factor for VCO * @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
@ -3946,20 +3993,6 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
} }
/**
* @brief Get the oscillator used as PLL clock source.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_MSI
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
}
/** /**
* @brief Get Division factor for the main PLL and other PLL * @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider

70
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_rtc.h
View file

@ -1158,10 +1158,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/ */
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
} }
/** /**
@ -1196,10 +1193,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/ */
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)))>> RTC_TR_MNU_Pos);
temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
} }
/** /**
@ -1234,10 +1228,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/ */
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos);
temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
} }
/** /**
@ -1430,10 +1421,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
*/ */
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
} }
/** /**
@ -1526,10 +1514,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
*/ */
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos);
temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
} }
/** /**
@ -1559,10 +1544,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/ */
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
} }
/** /**
@ -1759,10 +1741,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
} }
/** /**
@ -1854,10 +1833,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
} }
/** /**
@ -1885,10 +1861,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
} }
/** /**
@ -1916,10 +1889,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
} }
/** /**
@ -2137,10 +2107,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
} }
/** /**
@ -2232,10 +2199,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
} }
/** /**
@ -2263,10 +2227,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
} }
/** /**
@ -2294,10 +2255,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
*/ */
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
{ {
register uint32_t temp = 0U; return ((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
} }
/** /**

16
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_sdmmc.h
View file

@ -34,8 +34,8 @@
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_LL_SDMMC_H #ifndef STM32L4xx_LL_SDMMC_H
#define __STM32L4xx_LL_SDMMC_H #define STM32L4xx_LL_SDMMC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -421,9 +421,9 @@ typedef struct
*/ */
#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400) #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
#else #else
#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU)
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/** /**
* @} * @}
@ -447,7 +447,7 @@ typedef struct
/** @defgroup SDMMC_LL_Command_Index Command Index /** @defgroup SDMMC_LL_Command_Index Command Index
* @{ * @{
*/ */
#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/** /**
* @} * @}
*/ */
@ -525,7 +525,7 @@ typedef struct
/** @defgroup SDMMC_LL_Data_Length Data Lenght /** @defgroup SDMMC_LL_Data_Length Data Lenght
* @{ * @{
*/ */
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/** /**
* @} * @}
*/ */
@ -946,7 +946,7 @@ typedef struct
* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
* @retval The new state of SDMMC_FLAG (SET or RESET). * @retval The new state of SDMMC_FLAG (SET or RESET).
*/ */
#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/** /**
@ -1229,6 +1229,6 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
} }
#endif #endif
#endif /* __STM32L4xx_LL_SDMMC_H */ #endif /* STM32L4xx_LL_SDMMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

42
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_spi.h
View file

@ -397,7 +397,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
} }
/** /**
@ -738,7 +738,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
} }
/** /**
@ -902,7 +902,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)); return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
} }
/** /**
@ -921,7 +921,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
} }
/** /**
@ -932,7 +932,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
} }
/** /**
@ -943,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
} }
/** /**
@ -954,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
} }
/** /**
@ -965,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
} }
/** /**
@ -983,7 +983,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
} }
/** /**
@ -994,7 +994,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
} }
/** /**
@ -1170,7 +1170,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
} }
/** /**
@ -1181,7 +1181,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
} }
/** /**
@ -1192,7 +1192,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
} }
/** /**
@ -1233,7 +1233,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
} }
/** /**
@ -1266,7 +1266,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{ {
return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
} }
/** /**
@ -1373,7 +1373,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
*/ */
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{ {
#if defined (__GNUC__)
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
*spidr = TxData;
#else
*((__IO uint8_t *)&SPIx->DR) = TxData; *((__IO uint8_t *)&SPIx->DR) = TxData;
#endif
} }
/** /**
@ -1385,7 +1390,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
*/ */
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{ {
SPIx->DR = TxData; #if defined (__GNUC__)
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
*spidr = TxData;
#else
*((__IO uint16_t *)&SPIx->DR) = TxData;
#endif
} }
/** /**

2
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_swpmi.h
View file

@ -1154,7 +1154,7 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
* @} * @}
*/ */
#endif /* defined (SWPMI1) */ #endif /* SWPMI1 */
/** /**
* @} * @}

139
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_tim.h
View file

@ -127,14 +127,13 @@ static const uint8_t SHIFT_TAB_OISx[] =
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants /** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{ * @{
*/ */
/* Defines used for the bit position in the register and perform offsets */ /* Defines used for the bit position in the register and perform offsets */
#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FU)
/* Generic bit definitions for TIMx_OR2 register */ /* Generic bit definitions for TIMx_OR2 register */
#define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */
@ -179,16 +178,16 @@ static const uint8_t SHIFT_TAB_OISx[] =
#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
#define DT_DELAY_1 ((uint8_t)0x7FU) #define DT_DELAY_1 ((uint8_t)0x7F)
#define DT_DELAY_2 ((uint8_t)0x3FU) #define DT_DELAY_2 ((uint8_t)0x3F)
#define DT_DELAY_3 ((uint8_t)0x1FU) #define DT_DELAY_3 ((uint8_t)0x1F)
#define DT_DELAY_4 ((uint8_t)0x1FU) #define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
#define DT_RANGE_1 ((uint8_t)0x00U) #define DT_RANGE_1 ((uint8_t)0x00)
#define DT_RANGE_2 ((uint8_t)0x80U) #define DT_RANGE_2 ((uint8_t)0x80)
#define DT_RANGE_3 ((uint8_t)0xC0U) #define DT_RANGE_3 ((uint8_t)0xC0)
#define DT_RANGE_4 ((uint8_t)0xE0U) #define DT_RANGE_4 ((uint8_t)0xE0)
/** Legacy definitions for compatibility purpose /** Legacy definitions for compatibility purpose
@cond 0 @cond 0
@ -836,9 +835,9 @@ typedef struct
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{ * @{
*/ */
#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
/** /**
* @} * @}
*/ */
@ -1058,7 +1057,9 @@ typedef struct
#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
#if defined(DFSDM1_Channel0)
#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
#endif /* DFSDM1_Channel0 */
/** /**
* @} * @}
*/ */
@ -1322,7 +1323,7 @@ typedef struct
* @param __VALUE__ Value to be written in the register * @param __VALUE__ Value to be written in the register
* @retval None * @retval None
*/ */
#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/** /**
* @brief Read a value in TIM register. * @brief Read a value in TIM register.
@ -1330,7 +1331,7 @@ typedef struct
* @param __REG__ Register to be read * @param __REG__ Register to be read
* @retval Register value * @retval Register value
*/ */
#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/** /**
* @} * @}
*/ */
@ -1338,6 +1339,7 @@ typedef struct
/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
* @{ * @{
*/ */
/** /**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@ -1362,9 +1364,9 @@ typedef struct
*/ */
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
(((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
(((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
(((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U) 0U)
/** /**
@ -1474,7 +1476,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
} }
/** /**
@ -1507,7 +1509,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
} }
/** /**
@ -1576,6 +1578,9 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported * check whether or not the counter mode selection feature is supported
* by a timer instance. * by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
* requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode * CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance * @param TIMx Timer instance
@ -1589,7 +1594,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{ {
MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
} }
/** /**
@ -1642,7 +1647,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
} }
/** /**
@ -2009,7 +2014,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
*/ */
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{ {
return (READ_BIT(TIMx->CCER, Channels) == (Channels)); return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
} }
/** /**
@ -2353,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return (READ_BIT(*pReg, bitfield) == bitfield); return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
} }
/** /**
@ -2429,7 +2434,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return (READ_BIT(*pReg, bitfield) == bitfield); return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
} }
/** /**
@ -2514,11 +2519,11 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return (READ_BIT(*pReg, bitfield) == bitfield); return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
} }
/** /**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance. * dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@ -3058,7 +3063,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
} }
/** /**
@ -3169,7 +3174,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
} }
/** /**
@ -3349,7 +3354,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
} }
/** /**
@ -3594,7 +3599,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
} }
/** /**
@ -3637,7 +3642,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
} }
/** /**
@ -3651,7 +3656,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
* OR3 BK2INE LL_TIM_EnableBreakInputSource\n * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
* OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
* OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
* OR3 BK2DF1BK0E LL_TIM_EnableBreakInputSource * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
* @param TIMx Timer instance * @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values: * @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN
@ -3680,7 +3685,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
* OR3 BK2INE LL_TIM_DisableBreakInputSource\n * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
* OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
* OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
* OR3 BK2DF1BK0E LL_TIM_DisableBreakInputSource * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
* @param TIMx Timer instance * @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values: * @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN * @arg @ref LL_TIM_BREAK_INPUT_BKIN
@ -3725,7 +3730,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
uint32_t Polarity) uint32_t Polarity)
{ {
register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
} }
/** /**
* @} * @}
@ -3789,7 +3794,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
*/ */
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{ {
MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
} }
/** /**
@ -4032,7 +4037,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
} }
/** /**
@ -4054,7 +4059,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
} }
/** /**
@ -4076,7 +4081,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
} }
/** /**
@ -4098,7 +4103,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
} }
/** /**
@ -4120,7 +4125,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
} }
/** /**
@ -4142,7 +4147,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
} }
/** /**
@ -4164,7 +4169,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
} }
/** /**
@ -4186,7 +4191,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
} }
/** /**
@ -4208,7 +4213,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
} }
/** /**
@ -4230,7 +4235,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
} }
/** /**
@ -4252,7 +4257,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
} }
/** /**
@ -4274,7 +4279,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
} }
/** /**
@ -4296,7 +4301,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
} }
/** /**
@ -4318,7 +4323,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
} }
/** /**
@ -4340,7 +4345,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
} }
/** /**
@ -4362,7 +4367,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
} }
/** /**
@ -4402,7 +4407,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
} }
/** /**
@ -4435,7 +4440,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
} }
/** /**
@ -4468,7 +4473,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
} }
/** /**
@ -4501,7 +4506,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
} }
/** /**
@ -4534,7 +4539,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
} }
/** /**
@ -4567,7 +4572,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
} }
/** /**
@ -4600,7 +4605,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
} }
/** /**
@ -4633,7 +4638,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
} }
/** /**
@ -4673,7 +4678,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
} }
/** /**
@ -4706,7 +4711,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
} }
/** /**
@ -4739,7 +4744,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
} }
/** /**
@ -4772,7 +4777,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
} }
/** /**
@ -4805,7 +4810,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
} }
/** /**
@ -4838,7 +4843,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
} }
/** /**
@ -4871,7 +4876,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
*/ */
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{ {
return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
} }
/** /**

104
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usart.h
View file

@ -115,8 +115,8 @@ typedef struct
This parameter can be a value of @ref USART_LL_EC_PRESCALER. This parameter can be a value of @ref USART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
#endif #endif
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
@ -202,7 +202,7 @@ typedef struct
*/ */
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
@ -630,15 +630,14 @@ typedef struct
* @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256 * @arg @ref LL_USART_PRESCALER_DIV256
* @param __PRESCALER__ Prescaler value
@endif @endif
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#else #else
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#endif #endif
/** /**
@ -659,15 +658,14 @@ typedef struct
* @arg @ref LL_USART_PRESCALER_DIV64 * @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256 * @arg @ref LL_USART_PRESCALER_DIV256
* @param __PRESCALER__ Prescaler value
@endif @endif
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/ */
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#else #else
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
#endif #endif
/** /**
@ -725,7 +723,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief FIFO Mode Enable * @brief FIFO Mode Enable
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -914,6 +911,43 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
} }
#if defined(USART_CR3_UCESM)
/**
* @brief USART Clock enabled in STOP Mode
* @note When this function is called, USART Clock is enabled while in STOP mode
* @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief USART clock disabled in STOP Mode
* @note When this function is called, USART Clock is disabled while in STOP mode
* @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM);
}
/**
* @brief Indicate if USART clock is enabled in STOP Mode
* @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx)
{
return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM));
}
#endif /* USART_CR3_UCESM */
/** /**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx * @rmtoll CR1 RE LL_USART_EnableDirectionRx
@ -1267,7 +1301,6 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
} }
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
/** /**
* @brief Configure Clock source prescaler for baudrate generator and oversampling * @brief Configure Clock source prescaler for baudrate generator and oversampling
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -1291,7 +1324,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase,
*/ */
__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue); MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
} }
/** /**
@ -1962,7 +1995,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
if (OverSampling == LL_USART_OVERSAMPLING_8) if (OverSampling == LL_USART_OVERSAMPLING_8)
{ {
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate)); usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
#else #else
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
#endif #endif
@ -1973,7 +2006,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
else else
{ {
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate)); USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate));
#else #else
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
#endif #endif
@ -2017,7 +2050,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t Pe
register uint32_t usartdiv = 0x0U; register uint32_t usartdiv = 0x0U;
register uint32_t brrresult = 0x0U; register uint32_t brrresult = 0x0U;
#if defined(USART_PRESC_PRESCALER) #if defined(USART_PRESC_PRESCALER)
register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue])); register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
#endif #endif
usartdiv = USARTx->BRR; usartdiv = USARTx->BRR;
@ -2184,7 +2217,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
} }
/** /**
@ -2331,7 +2364,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
*/ */
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
} }
/** /**
@ -2429,7 +2462,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
*/ */
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature /** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
* @{ * @{
*/ */
@ -3066,7 +3098,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE #define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
@ -3108,7 +3139,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF #define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
@ -3202,7 +3232,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
} }
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
/** /**
* @brief Check if the SPI Slave Underrun error flag is set or not * @brief Check if the SPI Slave Underrun error flag is set or not
* @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
@ -3215,8 +3244,8 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)); return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR));
} }
#endif
#endif
/** /**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
* @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
@ -3323,7 +3352,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if the USART TX FIFO Empty Flag is set or not * @brief Check if the USART TX FIFO Empty Flag is set or not
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3352,7 +3380,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */ /* Function available only on devices supporting Transmit Complete before Guard Time feature */
/** /**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
@ -3367,7 +3394,6 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if the USART TX FIFO Threshold Flag is set or not * @brief Check if the USART TX FIFO Threshold Flag is set or not
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3418,14 +3444,14 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
} }
/** /**
* @brief Clear Noise detected Flag * @brief Clear Noise Error detected Flag
* @rmtoll ICR NCF LL_USART_ClearFlag_NE * @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @param USARTx USART Instance * @param USARTx USART Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
{ {
WRITE_REG(USARTx->ICR, USART_ICR_NCF); WRITE_REG(USARTx->ICR, USART_ICR_NECF);
} }
/** /**
@ -3451,7 +3477,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Clear TX FIFO Empty Flag * @brief Clear TX FIFO Empty Flag
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3478,7 +3503,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */ /* Function available only on devices supporting Transmit Complete before Guard Time feature */
/** /**
* @brief Clear Smartcard Transmission Complete Before Guard Time Flag * @brief Clear Smartcard Transmission Complete Before Guard Time Flag
@ -3543,7 +3567,6 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
} }
#if defined(USART_CR2_SLVEN) #if defined(USART_CR2_SLVEN)
/** /**
* @brief Clear SPI Slave Underrun Flag * @brief Clear SPI Slave Underrun Flag
* @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
@ -3556,8 +3579,8 @@ __STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
{ {
WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
} }
#endif
#endif
/** /**
* @brief Clear Character Match Flag * @brief Clear Character Match Flag
* @rmtoll ICR CMCF LL_USART_ClearFlag_CM * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
@ -3602,7 +3625,6 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE #define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
@ -3644,7 +3666,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF #define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
@ -3721,7 +3742,6 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Enable TX FIFO Empty Interrupt * @brief Enable TX FIFO Empty Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3802,7 +3822,6 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Enable TX FIFO Threshold Interrupt * @brief Enable TX FIFO Threshold Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3818,7 +3837,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */ /* Function available only on devices supporting Transmit Complete before Guard Time feature */
/** /**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
@ -3835,7 +3853,6 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Enable RX FIFO Threshold Interrupt * @brief Enable RX FIFO Threshold Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -3862,7 +3879,6 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE #define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
@ -3904,7 +3920,6 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF #define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
@ -3981,7 +3996,6 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Disable TX FIFO Empty Interrupt * @brief Disable TX FIFO Empty Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4064,7 +4078,6 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Disable TX FIFO Threshold Interrupt * @brief Disable TX FIFO Threshold Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4096,7 +4109,6 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Disable RX FIFO Threshold Interrupt * @brief Disable RX FIFO Threshold Interrupt
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4123,7 +4135,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE #define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
@ -4165,7 +4176,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/* Legacy define */ /* Legacy define */
#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF #define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
@ -4242,7 +4252,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4321,7 +4330,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
} }
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4337,7 +4345,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_TCBGT_SUPPORT) #if defined(USART_TCBGT_SUPPORT)
/* Function available only on devices supporting Transmit Complete before Guard Time feature */ /* Function available only on devices supporting Transmit Complete before Guard Time feature */
/** /**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
@ -4354,7 +4361,6 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
#endif #endif
#if defined(USART_CR1_FIFOEN) #if defined(USART_CR1_FIFOEN)
/** /**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
* @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
@ -4628,8 +4634,6 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
@else @else
* @brief Request a Transmit data flush * @brief Request a Transmit data flush
@endif @endif
* @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance * @param USARTx USART Instance
* @retval None * @retval None

343
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_usb.h
View file

@ -2,7 +2,7 @@
****************************************************************************** ******************************************************************************
* @file stm32l4xx_ll_usb.h * @file stm32l4xx_ll_usb.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of USB Core HAL module. * @brief Header file of USB Low Layer HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
@ -41,20 +41,16 @@
extern "C" { extern "C" {
#endif #endif
#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \
defined(STM32L452xx) || defined(STM32L462xx) || \
defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL #if defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup USB_Core /** @addtogroup USB_LL
* @{ * @{
*/ */
@ -68,27 +64,27 @@ typedef enum
USB_DEVICE_MODE = 0, USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1, USB_HOST_MODE = 1,
USB_DRD_MODE = 2 USB_DRD_MODE = 2
} USB_ModeTypeDef; } USB_ModeTypeDef;
#if defined (USB_OTG_FS) #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** /**
* @brief URB States definition * @brief URB States definition
*/ */
typedef enum { typedef enum
{
URB_IDLE = 0, URB_IDLE = 0,
URB_DONE, URB_DONE,
URB_NOTREADY, URB_NOTREADY,
URB_NYET, URB_NYET,
URB_ERROR, URB_ERROR,
URB_STALL URB_STALL
} USB_OTG_URBStateTypeDef; } USB_OTG_URBStateTypeDef;
/** /**
* @brief Host channel States definition * @brief Host channel States definition
*/ */
typedef enum { typedef enum
{
HC_IDLE = 0, HC_IDLE = 0,
HC_XFRC, HC_XFRC,
HC_HALTED, HC_HALTED,
@ -98,11 +94,10 @@ typedef enum {
HC_XACTERR, HC_XACTERR,
HC_BBLERR, HC_BBLERR,
HC_DATATGLERR HC_DATATGLERR
} USB_OTG_HCStateTypeDef; } USB_OTG_HCStateTypeDef;
/** /**
* @brief PCD Initialization Structure definition * @brief USB OTG Initialization Structure definition
*/ */
typedef struct typedef struct
{ {
@ -117,7 +112,7 @@ typedef struct
uint32_t speed; /*!< USB Core speed. uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */ This parameter can be any value of @ref USB_Core_Speed_ */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
This parameter can be any value of @ref USB_EP0_MPS_ */ This parameter can be any value of @ref USB_EP0_MPS_ */
@ -129,7 +124,7 @@ typedef struct
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
@ -138,7 +133,6 @@ typedef struct
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef; } USB_OTG_CfgTypeDef;
typedef struct typedef struct
@ -174,7 +168,6 @@ typedef struct
uint32_t xfer_len; /*!< Current transfer length */ uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef; } USB_OTG_EPTypeDef;
typedef struct typedef struct
@ -228,9 +221,8 @@ typedef struct
USB_OTG_HCStateTypeDef state; /*!< Host Channel state. USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef; } USB_OTG_HCTypeDef;
#endif /* USB_OTG_FS */ #endif /* defined USB_OTG_FS || USB_OTG_HS */
#if defined (USB) #if defined (USB)
/** /**
@ -245,8 +237,6 @@ typedef struct
uint32_t speed; /*!< USB Core speed. uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed */ This parameter can be any value of @ref USB_Core_Speed */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
This parameter can be any value of @ref USB_EP0_MPS */ This parameter can be any value of @ref USB_EP0_MPS */
@ -276,6 +266,9 @@ typedef struct
uint8_t type; /*!< Endpoint type uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */ This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
@ -309,168 +302,84 @@ typedef struct
/** @defgroup PCD_Exported_Constants PCD Exported Constants /** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{ * @{
*/ */
#if defined (USB_OTG_FS)
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @defgroup USB_Core_Mode_ USB Core Mode /** @defgroup USB_Core_Mode_ USB Core Mode
* @{ * @{
*/ */
#define USB_OTG_MODE_DEVICE 0 #define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1 #define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2 #define USB_OTG_MODE_DRD 2U
/** /**
* @} * @}
*/ */
/** @defgroup USB_Core_Speed_ USB Core Speed /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{ * @{
*/ */
#define USB_OTG_SPEED_HIGH 0 #define USB_OTG_SPEED_LOW 2U
#define USB_OTG_SPEED_HIGH_IN_FULL 1 #define USB_OTG_SPEED_FULL 3U
#define USB_OTG_SPEED_LOW 2
#define USB_OTG_SPEED_FULL 3
/** /**
* @} * @}
*/ */
/** @defgroup USB_Core_PHY_ USB Core PHY /** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{ * @{
*/ */
#define USB_OTG_EMBEDDED_PHY 1 #define USB_OTG_ULPI_PHY 1U
#define USB_OTG_EMBEDDED_PHY 2U
/** /**
* @} * @}
*/ */
/** @defgroup USB_Core_MPS_ USB Core MPS /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{ * @{
*/ */
#define USB_OTG_FS_MAX_PACKET_SIZE 64 #define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64 #define USB_OTG_MAX_EP0_SIZE 64U
/** /**
* @} * @}
*/ */
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{ * @{
*/ */
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) #define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/** /**
* @} * @}
*/ */
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval /** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{ * @{
*/ */
#define DCFG_FRAME_INTERVAL_80 0 #define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1 #define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2 #define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3 #define DCFG_FRAME_INTERVAL_95 3U
/** /**
* @} * @}
*/ */
/** @defgroup USB_EP0_MPS_ USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0
#define DEP0CTL_MPS_32 1
#define DEP0CTL_MPS_16 2
#define DEP0CTL_MPS_8 3
/**
* @}
*/
/** @defgroup USB_EP_Speed_ USB EP Speed
* @{
*/
#define EP_SPEED_LOW 0
#define EP_SPEED_FULL 1
#define EP_SPEED_HIGH 2
/**
* @}
*/
/** @defgroup USB_EP_Type_ USB EP Type
* @{
*/
#define EP_TYPE_CTRL 0
#define EP_TYPE_ISOC 1
#define EP_TYPE_BULK 2
#define EP_TYPE_INTR 3
#define EP_TYPE_MSK 3
/**
* @}
*/
/** @defgroup USB_STS_Defines_ USB STS Defines
* @{
*/
#define STS_GOUT_NAK 1
#define STS_DATA_UPDT 2
#define STS_XFER_COMP 3
#define STS_SETUP_COMP 4
#define STS_SETUP_UPDT 6
/**
* @}
*/
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
* @{
*/
#define HCFG_30_60_MHZ 0
#define HCFG_48_MHZ 1
#define HCFG_6_MHZ 2
/**
* @}
*/
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0
#define HPRT0_PRTSPD_FULL_SPEED 1
#define HPRT0_PRTSPD_LOW_SPEED 2
/**
* @}
*/
#define HCCHAR_CTRL 0
#define HCCHAR_ISOC 1
#define HCCHAR_BULK 2
#define HCCHAR_INTR 3
#define HC_PID_DATA0 0
#define HC_PID_DATA2 1
#define HC_PID_DATA1 2
#define HC_PID_SETUP 3
#define GRXSTS_PKTSTS_IN 2
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
#define GRXSTS_PKTSTS_CH_HALTED 7
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
#endif /* USB_OTG_FS */
#if defined (USB)
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{ * @{
*/ */
#define DEP0CTL_MPS_64 0 #define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1 #define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2 #define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3 #define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/** /**
* @} * @}
*/ */
@ -478,33 +387,125 @@ typedef struct
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type /** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{ * @{
*/ */
#define EP_TYPE_CTRL 0 #define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1 #define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2 #define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3 #define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3 #define EP_TYPE_MSK 3U
/** /**
* @} * @}
*/ */
#define BTABLE_ADDRESS (0x000) /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
#endif /* USB */ * @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* USB_OTG_FS || USB_OTG_HS */
#if defined (USB)
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
#endif /* USB */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#if defined (USB_OTG_FS) /** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) #define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) #define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) #define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) #define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* USB_OTG_FS */ #endif /* USB_OTG_FS || USB_OTG_HS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
#if defined (USB_OTG_FS) /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
@ -517,9 +518,9 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
@ -528,7 +529,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
@ -551,14 +552,14 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t speed, uint8_t speed,
uint8_t ep_type, uint8_t ep_type,
uint16_t mps); uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
#endif /* USB_OTG_FS */ #endif /* USB_OTG_FS || USB_OTG_HS */
#if defined (USB) #if defined (USB)
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
@ -571,7 +572,7 @@ HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma); HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
@ -580,7 +581,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup); HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
@ -601,11 +602,15 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
* @} * @}
*/ */
#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ /**
/* STM32L452xx || STM32L462xx || */ * @}
/* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ /**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus #ifdef __cplusplus
} }

4
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_utils.h
View file

@ -246,7 +246,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
*/ */
__STATIC_INLINE uint32_t LL_GetFlashSize(void) __STATIC_INLINE uint32_t LL_GetFlashSize(void)
{ {
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
} }
/** /**
@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
*/ */
__STATIC_INLINE uint32_t LL_GetPackageType(void) __STATIC_INLINE uint32_t LL_GetPackageType(void)
{ {
return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
} }
/** /**

20
ext/hal/st/stm32cube/stm32l4xx/drivers/include/stm32l4xx_ll_wwdg.h
View file

@ -49,25 +49,20 @@ extern "C" {
*/ */
#if defined (WWDG) #if defined (WWDG)
/** @defgroup WWDG_LL WWDG /** @defgroup WWDG_LL WWDG
* @{ * @{
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{ * @{
*/ */
/** @defgroup WWDG_LL_EC_IT IT Defines /** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{ * @{
@ -80,7 +75,7 @@ extern "C" {
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{ * @{
*/ */
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
@ -119,7 +114,6 @@ extern "C" {
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@ -155,7 +149,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
*/ */
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{ {
return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
} }
/** /**
@ -182,7 +176,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
*/ */
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{ {
return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T)); return (READ_BIT(WWDGx->CR, WWDG_CR_T));
} }
/** /**
@ -215,7 +209,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale
*/ */
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{ {
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
} }
/** /**
@ -247,7 +241,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
*/ */
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{ {
return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W)); return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
} }
/** /**
@ -268,7 +262,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
*/ */
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{ {
return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
} }
/** /**
@ -310,7 +304,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
*/ */
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{ {
return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
} }
/** /**

2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal.c
View file

@ -69,7 +69,7 @@
*/ */
#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ #define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ #define __STM32L4xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ #define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
|(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\

453
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_adc.c
View file

@ -211,6 +211,79 @@
[..] [..]
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
(+) ErrorCallback : ADC error callback
(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
(+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
(+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
(+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
(+) EndOfSamplingCallback : ADC end of sampling callback
(+) MspInitCallback : ADC Msp Init callback
(+) MspDeInitCallback : ADC Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
(+) ErrorCallback : ADC error callback
(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
(+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
(+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
(+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
(+) EndOfSamplingCallback : ADC end of sampling callback
(+) MspInitCallback : ADC Msp Init callback
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
or @ref HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -269,37 +342,22 @@
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
when no regular conversion is on-going */ when no regular conversion is on-going */
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\ /* Timeout values for ADC operations (enable settling time, */
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ /* disable settling time, ...). */
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion /* Values defined to be higher than worst cases: low clock frequency, */
(neither regular nor injected) is on-going */ /* maximum prescalers. */
/* Delay to wait before setting ADEN once ADCAL has been reset
must be at least 4 ADC clock cycles.
Assuming lowest ADC clock (140 KHz according to DS), this
4 ADC clock cycles duration is equal to
4 / 140,000 = 0.028 ms.
ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
the 4 ADC clock cycles have elapsed while waiting for ADRDY
to become 1 */
#define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */
#define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */
/* Timeout to wait for current conversion on going to be completed. */ /* Timeout to wait for current conversion on going to be completed. */
/* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */
/* - maximum sampling time (640.5 adc_clk) */ /* - maximum sampling time (640.5 adc_clk) */
/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
/* - ADC clock with prescaler 256 */ /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
/* (from asynchronous clock, assuming clock frequency same as CPU for */
/* this calculation) */
/* - ADC oversampling ratio 256 */ /* - ADC oversampling ratio 256 */
/* Calculation: 653 * 256 * 256 = 42795008 CPU clock cycles max */ /* Calculation: 653 * 4096 * 256 CPU clock cycles max */
/* Unit: cycles of CPU clock. */ /* Unit: cycles of CPU clock. */
#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 42795008) /*!< ADC conversion completion time-out value */ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 653U * 4096U * 256U) /*!< ADC conversion completion time-out value */
/** /**
@ -403,8 +461,29 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
/* - Initialization of ADC MSP */ /* - Initialization of ADC MSP */
if(hadc->State == HAL_ADC_STATE_RESET) if(hadc->State == HAL_ADC_STATE_RESET)
{ {
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Init the ADC Callback settings */
hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
if (hadc->MspInitCallback == NULL)
{
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */ /* Init the low level hardware */
HAL_ADC_MspInit(hadc); HAL_ADC_MspInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */ /* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc); ADC_CLEAR_ERRORCODE(hadc);
@ -784,7 +863,18 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
the clock will reset all ADCs. the clock will reset all ADCs.
*/ */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
if (hadc->MspDeInitCallback == NULL)
{
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: RCC clock, NVIC */
hadc->MspDeInitCallback(hadc);
#else
/* DeInit the low level hardware: RCC clock, NVIC */
HAL_ADC_MspDeInit(hadc); HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */ /* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc); ADC_CLEAR_ERRORCODE(hadc);
@ -835,6 +925,250 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
*/ */
} }
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User ADC Callback
* To be used instead of the weak predefined callback
* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
* @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
* @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if ((hadc->State & HAL_ADC_STATE_READY) != 0)
{
switch (CallbackID)
{
case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
hadc->ConvCpltCallback = pCallback;
break;
case HAL_ADC_CONVERSION_HALF_CB_ID :
hadc->ConvHalfCpltCallback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
hadc->LevelOutOfWindowCallback = pCallback;
break;
case HAL_ADC_ERROR_CB_ID :
hadc->ErrorCallback = pCallback;
break;
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = pCallback;
break;
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
hadc->LevelOutOfWindow3Callback = pCallback;
break;
case HAL_ADC_END_OF_SAMPLING_CB_ID :
hadc->EndOfSamplingCallback = pCallback;
break;
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = pCallback;
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_ADC_STATE_RESET == hadc->State)
{
switch (CallbackID)
{
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = pCallback;
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a ADC Callback
* ADC callback is redirected to the weak predefined callback
* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
* @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
* @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if ((hadc->State & HAL_ADC_STATE_READY) != 0)
{
switch (CallbackID)
{
case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
break;
case HAL_ADC_CONVERSION_HALF_CB_ID :
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
break;
case HAL_ADC_ERROR_CB_ID :
hadc->ErrorCallback = HAL_ADC_ErrorCallback;
break;
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
break;
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
break;
case HAL_ADC_END_OF_SAMPLING_CB_ID :
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
break;
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_ADC_STATE_RESET == hadc->State)
{
switch (CallbackID)
{
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1554,7 +1888,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
* HAL_ADCEx_MultiModeStart_DMA() function must be used. * HAL_ADCEx_MultiModeStart_DMA() function must be used.
* @param hadc ADC handle * @param hadc ADC handle
* @param pData Destination Buffer address. * @param pData Destination Buffer address.
* @param Length Length of data to be transferred from ADC peripheral to memory (in bytes) * @param Length Number of data to be transferred from ADC peripheral to memory
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@ -1805,7 +2139,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
} }
/* End Of Sampling callback */ /* End Of Sampling callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->EndOfSamplingCallback(hadc);
#else
HAL_ADCEx_EndOfSamplingCallback(hadc); HAL_ADCEx_EndOfSamplingCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */ /* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
@ -1883,7 +2221,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* to determine if conversion has been triggered from EOC or EOS, */ /* to determine if conversion has been triggered from EOC or EOS, */
/* possibility to use: */ /* possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc); HAL_ADC_ConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */ /* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
@ -1971,7 +2313,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
interruption has been triggered by end of conversion or end of interruption has been triggered by end of conversion or end of
sequence. */ sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc); HAL_ADCEx_InjectedConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */ /* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
@ -1984,7 +2330,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window 1 callback */ /* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc); HAL_ADC_LevelOutOfWindowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */ /* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
} }
@ -1996,7 +2347,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
/* Level out of window 2 callback */ /* Level out of window 2 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow2Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow2Callback(hadc); HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */ /* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
} }
@ -2008,7 +2364,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
/* Level out of window 3 callback */ /* Level out of window 3 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow3Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow3Callback(hadc); HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */ /* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
} }
@ -2062,7 +2423,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* flag OVR is reset. */ /* flag OVR is reset. */
/* Therefore, old ADC conversion data can be retrieved in */ /* Therefore, old ADC conversion data can be retrieved in */
/* function "HAL_ADC_ErrorCallback()". */ /* function "HAL_ADC_ErrorCallback()". */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc); HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
/* Clear ADC overrun flag */ /* Clear ADC overrun flag */
@ -2081,8 +2446,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Clear the Injected context queue overflow flag */ /* Clear the Injected context queue overflow flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
/* Error callback */ /* Injected context queue overflow callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedQueueOverflowCallback(hadc);
#else
HAL_ADCEx_InjectedQueueOverflowCallback(hadc); HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
} }
@ -2319,7 +2688,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Parameters update conditioned to ADC state: */ /* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */ /* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */ /* - Single or differential mode */
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (ADC_IS_ENABLE(hadc) == RESET) if (ADC_IS_ENABLE(hadc) == RESET)
{ {
/* Set mode single-ended or differential input of the selected ADC channel */ /* Set mode single-ended or differential input of the selected ADC channel */
@ -2332,6 +2700,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime);
} }
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */ /* If internal channel selected, enable dedicated internal buffers and */
/* paths. */ /* paths. */
@ -2351,11 +2721,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{ {
/* Configuration of common ADC parameters (continuation) */ /* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
/* of the common group are disabled. */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
{
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{ {
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
@ -2388,18 +2753,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
} }
} }
} }
/* If the requested internal measurement path has already been */
/* enabled and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
}
}
} }
/* If a conversion is on going on regular group, no update on regular */ /* If a conversion is on going on regular group, no update on regular */
@ -3012,14 +3365,22 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
} }
/* Conversion complete callback */ /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc); HAL_ADC_ConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
else /* DMA and-or internal error occurred */ else /* DMA and-or internal error occurred */
{ {
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
{ {
/* Call HAL ADC Error Callback function */ /* Call HAL ADC Error Callback function */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc); HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
else else
{ {
@ -3040,7 +3401,11 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Half conversion callback */ /* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc); HAL_ADC_ConvHalfCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
/** /**
@ -3060,7 +3425,11 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma)
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
/* Error callback */ /* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc); HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} }
/** /**

48
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_adc_ex.c
View file

@ -81,22 +81,14 @@
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
once the ADC is enabled */ once the ADC is enabled */
#define ADC_CFGR2_INJ_FIELDS ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR |\
ADC_CFGR2_OVSS )) /*!< ADC_CFGR2 injected oversampling parameters that can be updated
when no conversion is on-going (neither regular nor injected) */
#define ADC_OFR_INJ_FIELDS ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
/* Fixed timeout value for ADC calibration. */ /* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: low clock frequency, */ /* Values defined to be higher than worst cases: maximum ratio between ADC */
/* maximum prescalers. */ /* and CPU clock frequencies. */
/* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value */ /* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */
/* according to Data sheet), calibration_time MAX = 112 / f_ADC */ /* source PLL SAI 8MHz, ADC clock prescaler 256), CPU frequency 80MHz. */
/* 112 / 140,000 = 0.8 ms */ /* Calibration time max = 116 / fADC (refer to datasheet) */
/* At maximum CPU speed (80 MHz), this means */ /* = 296 960 CPU cycles */
/* 0.8 ms * 80 MHz = 64000 CPU cycles */ #define ADC_CALIBRATION_TIMEOUT (296960U) /*!< ADC calibration time-out value (unit: CPU cycles) */
#define ADC_CALIBRATION_TIMEOUT (64000U) /*!< ADC calibration time-out value */
/** /**
* @} * @}
@ -1067,6 +1059,10 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning if no assert_param check */
/* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
UNUSED(hadc);
/* Pointer to the common control register */ /* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
@ -1927,7 +1923,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Parameters update conditioned to ADC state: */ /* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */ /* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */ /* - Single or differential mode */
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (ADC_IS_ENABLE(hadc) == RESET) if (ADC_IS_ENABLE(hadc) == RESET)
{ {
/* Set mode single-ended or differential input of the selected ADC channel */ /* Set mode single-ended or differential input of the selected ADC channel */
@ -1940,6 +1935,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime); LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1), sConfigInjected->InjectedSamplingTime);
} }
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
/* internal measurement paths enable: If internal channel selected, */ /* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */ /* enable dedicated internal buffers and path. */
@ -1956,12 +1953,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U))
) )
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
/* of the common group are disabled. */
if ((ADC_IS_ENABLE(hadc) == RESET) &&
(ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
{ {
if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
{ {
@ -1993,19 +1984,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
} }
} }
} }
/* If the requested internal measurement path has already been enabled */
/* and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
}
}
/* Process unlocked */ /* Process unlocked */
__HAL_UNLOCK(hadc); __HAL_UNLOCK(hadc);

2923
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_can.c
View file

File diff suppressed because it is too large Load diff

274
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_comp.c
View file

@ -85,6 +85,63 @@
(#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
The only way to unlock the comparator is a device hardware reset. The only way to unlock the comparator is a device hardware reset.
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_COMP_RegisterCallback()
to register an interrupt callback.
[..]
Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
weak function.
[..]
@ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
all callbacks are set to the corresponding weak functions:
example @ref HAL_COMP_TriggerCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
or @ref HAL_COMP_Init() function.
[..]
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
@ -149,14 +206,14 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h" #include "stm32l4xx_hal.h"
#ifdef HAL_COMP_MODULE_ENABLED
#if defined (COMP1) || defined (COMP2)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
#ifdef HAL_COMP_MODULE_ENABLED
#if defined (COMP1) || defined (COMP2)
/** @defgroup COMP COMP /** @defgroup COMP COMP
* @brief COMP HAL module driver * @brief COMP HAL module driver
* @{ * @{
@ -248,6 +305,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED; hcomp->Lock = HAL_UNLOCKED;
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
/* Init SYSCFG and the low level hardware to access comparators */ /* Init SYSCFG and the low level hardware to access comparators */
/* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */ /* Note: HAL_COMP_Init() calls __HAL_RCC_SYSCFG_CLK_ENABLE() */
/* to enable internal control clock of the comparators. */ /* to enable internal control clock of the comparators. */
@ -259,8 +319,21 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* in "HAL_COMP_MspInit()". */ /* in "HAL_COMP_MspInit()". */
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
if (hcomp->MspInitCallback == NULL)
{
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hcomp->MspInitCallback(hcomp);
#else
/* Init the low level hardware */ /* Init the low level hardware */
HAL_COMP_MspInit(hcomp); HAL_COMP_MspInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} }
/* Memorize voltage scaler state before initialization */ /* Memorize voltage scaler state before initialization */
@ -415,8 +488,18 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
/* Set COMP_CSR register to reset value */ /* Set COMP_CSR register to reset value */
WRITE_REG(hcomp->Instance->CSR, 0x00000000U); WRITE_REG(hcomp->Instance->CSR, 0x00000000U);
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */ #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
if (hcomp->MspDeInitCallback == NULL)
{
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
hcomp->MspDeInitCallback(hcomp);
#else
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
HAL_COMP_MspDeInit(hcomp); HAL_COMP_MspDeInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/* Set HAL COMP handle state */ /* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_RESET; hcomp->State = HAL_COMP_STATE_RESET;
@ -458,6 +541,166 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
*/ */
} }
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User COMP Callback
* To be used instead of the weak predefined callback
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
* the configuration information for the specified COMP.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (HAL_COMP_STATE_READY == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = pCallback;
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_COMP_STATE_RESET == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a COMP Callback
* COMP callback is redirected to the weak predefined callback
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
* the configuration information for the specified COMP.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_COMP_STATE_READY == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_COMP_STATE_RESET == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -593,7 +836,11 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
} }
/* COMP trigger user callback */ /* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp); HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} }
} }
@ -679,7 +926,7 @@ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
} }
/** /**
* @brief Comparator callback. * @brief Comparator trigger callback.
* @param hcomp COMP handle * @param hcomp COMP handle
* @retval None * @retval None
*/ */
@ -733,8 +980,17 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
} }
/** /**
* @} * @brief Return the COMP error code.
* @param hcomp COMP handle
* @retval COMP error code
*/ */
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return hcomp->ErrorCode;
}
/** /**
* @} * @}
@ -752,4 +1008,8 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
#endif /* HAL_COMP_MODULE_ENABLED */ #endif /* HAL_COMP_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

49
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cortex.c
View file

@ -335,6 +335,9 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPre
*/ */
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */ /* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn); NVIC_SetPendingIRQ(IRQn);
} }
@ -350,6 +353,9 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/ */
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */ /* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn); return NVIC_GetPendingIRQ(IRQn);
} }
@ -363,6 +369,9 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/ */
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */ /* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn); NVIC_ClearPendingIRQ(IRQn);
} }
@ -424,6 +433,46 @@ __weak void HAL_SYSTICK_Callback(void)
} }
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0U;
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU settings take effects */
__DSB();
__ISB();
}
/** /**
* @brief Initialize and configure the Region and the memory to be protected. * @brief Initialize and configure the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains

101
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc.c
View file

@ -4,7 +4,7 @@
* @author MCD Application Team * @author MCD Application Team
* @brief CRC HAL module driver. * @brief CRC HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the CRC peripheral: * functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions * + Initialization and de-initialization functions
* + Peripheral Control functions * + Peripheral Control functions
* + Peripheral State functions * + Peripheral State functions
@ -113,7 +113,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
/** /**
* @brief Initialize the CRC according to the specified * @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle. * parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@ -131,7 +131,6 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{ {
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED; hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */ /* Init the low level hardware */
HAL_CRC_MspInit(hcrc); HAL_CRC_MspInit(hcrc);
} }
@ -190,7 +189,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/** /**
* @brief DeInitialize the CRC peripheral. * @brief DeInitialize the CRC peripheral.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@ -234,7 +233,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/** /**
* @brief Initializes the CRC MSP. * @brief Initializes the CRC MSP.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval None * @retval None
*/ */
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@ -249,7 +248,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
/** /**
* @brief DeInitialize the CRC MSP. * @brief DeInitialize the CRC MSP.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval None * @retval None
*/ */
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@ -275,7 +274,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using the combination of the previous CRC value and the new one using combination of the previous CRC value and the new one.
[..] or [..] or
@ -289,10 +288,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/** /**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value. * starting with the previously computed CRC as initialization value.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat. * provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t). * number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter. * @note By default, the API expects a uint32_t pointer as input buffer parameter.
@ -303,8 +302,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
*/ */
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{ {
uint32_t index = 0; /* CRC input data buffer index */ uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */ /* Process locked */
__HAL_LOCK(hcrc); __HAL_LOCK(hcrc);
@ -316,7 +315,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
{ {
case CRC_INPUTDATA_FORMAT_WORDS: case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */ /* Enter Data to the CRC calculator */
for(index = 0; index < BufferLength; index++) for (index = 0U; index < BufferLength; index++)
{ {
hcrc->Instance->DR = pBuffer[index]; hcrc->Instance->DR = pBuffer[index];
} }
@ -330,7 +329,6 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
case CRC_INPUTDATA_FORMAT_HALFWORDS: case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength); temp = CRC_Handle_16(hcrc, (uint16_t *)pBuffer, BufferLength);
break; break;
default: default:
break; break;
} }
@ -345,14 +343,13 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
return temp; return temp;
} }
/** /**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value. * starting with hcrc->Instance->INIT as initialization value.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat. * provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t). * number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter. * @note By default, the API expects a uint32_t pointer as input buffer parameter.
@ -363,8 +360,8 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
*/ */
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{ {
uint32_t index = 0; /* CRC input data buffer index */ uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */ /* Process locked */
__HAL_LOCK(hcrc); __HAL_LOCK(hcrc);
@ -380,7 +377,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
{ {
case CRC_INPUTDATA_FORMAT_WORDS: case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */ /* Enter 32-bit input data to the CRC calculator */
for(index = 0; index < BufferLength; index++) for (index = 0U; index < BufferLength; index++)
{ {
hcrc->Instance->DR = pBuffer[index]; hcrc->Instance->DR = pBuffer[index];
} }
@ -431,7 +428,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/** /**
* @brief Return the CRC handle state. * @brief Return the CRC handle state.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @retval HAL state * @retval HAL state
*/ */
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
@ -448,44 +445,54 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
* @} * @}
*/ */
/** @defgroup CRC_Private_Functions CRC Private Functions /** @addtogroup CRC_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief Enter 8-bit input data to the CRC calculator. * @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time. * Specific data handling to optimize processing time.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer * @param pBuffer pointer to the input data buffer
* @param BufferLength: input data buffer length * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{ {
uint32_t i = 0; /* input data buffer index */ uint32_t i; /* input data buffer index */
uint16_t data;
__IO uint16_t *pReg;
/* Processing time optimization: 4 bytes are entered in a row with a single word write, /* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type * last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the IP */ * handling by the IP */
for(i = 0; i < (BufferLength/4); i++) for (i = 0U; i < (BufferLength / 4U); i++)
{ {
hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3]; hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
((uint32_t)pBuffer[4U * i + 1U] << 16U) | \
((uint32_t)pBuffer[4U * i + 2U] << 8U) | \
(uint32_t)pBuffer[4U * i + 3U];
} }
/* last bytes specific handling */ /* last bytes specific handling */
if ((BufferLength%4) != 0) if ((BufferLength % 4U) != 0U)
{ {
if (BufferLength%4 == 1) if (BufferLength % 4U == 1U)
{ {
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i]; *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];
} }
if (BufferLength%4 == 2) if (BufferLength % 4U == 2U)
{ {
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);
*pReg = data;
} }
if (BufferLength%4 == 3) if (BufferLength % 4U == 3U)
{ {
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; data = (uint16_t)(pBuffer[4U * i] << 8U) | (uint16_t)pBuffer[4U * i + 1U];
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);
*pReg = data;
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i + 2U];
} }
} }
@ -493,30 +500,30 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
return hcrc->Instance->DR; return hcrc->Instance->DR;
} }
/** /**
* @brief Enter 16-bit input data to the CRC calculator. * @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time. * Specific data handling to optimize processing time.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param pBuffer: pointer to the input data buffer * @param pBuffer pointer to the input data buffer
* @param BufferLength: input data buffer length * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/ */
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{ {
uint32_t i = 0; /* input data buffer index */ uint32_t i; /* input data buffer index */
__IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write, /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the IP */ * a correct type handling by the IP */
for(i = 0; i < (BufferLength/2); i++) for (i = 0U; i < (BufferLength / 2U); i++)
{ {
hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1]; hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[2U * i + 1U];
} }
if ((BufferLength%2) != 0) if ((BufferLength % 2U) != 0U)
{ {
*(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);
*pReg = pBuffer[2U * i];
} }
/* Return the CRC computed value */ /* Return the CRC computed value */

38
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_crc_ex.c
View file

@ -89,12 +89,12 @@
/** /**
* @brief Initialize the CRC polynomial if different from default one. * @brief Initialize the CRC polynomial if different from default one.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long). * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g. * This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength: CRC polynomial length. * @param PolyLength CRC polynomial length.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
@ -104,7 +104,8 @@
*/ */
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{ {
uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */ HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */ /* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength)); assert_param(IS_CRC_POL_LENGTH(PolyLength));
@ -116,49 +117,54 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
* Look for MSB position: msb will contain the degree of * Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for * the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while (((Pol & (1U << msb)) == 0) && (msb-- > 0)) {} while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << msb)) == 0U))
{
}
switch (PolyLength) switch (PolyLength)
{ {
case CRC_POLYLENGTH_7B: case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B) if (msb >= HAL_CRC_LENGTH_7B)
{ {
return HAL_ERROR; status = HAL_ERROR;
} }
break; break;
case CRC_POLYLENGTH_8B: case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B) if (msb >= HAL_CRC_LENGTH_8B)
{ {
return HAL_ERROR; status = HAL_ERROR;
} }
break; break;
case CRC_POLYLENGTH_16B: case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B) if (msb >= HAL_CRC_LENGTH_16B)
{ {
return HAL_ERROR; status = HAL_ERROR;
} }
break; break;
case CRC_POLYLENGTH_32B: case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */ /* no polynomial definition vs. polynomial length issue possible */
break; break;
default: default:
return HAL_ERROR; status = HAL_ERROR;
break;
} }
if (status == HAL_OK)
{
/* set generating polynomial */ /* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol); WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */ /* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */ /* Return function status */
return HAL_OK; return status;
} }
/** /**
* @brief Set the Reverse Input data mode. * @brief Set the Reverse Input data mode.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param InputReverseMode: Input Data inversion mode. * @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
@ -185,8 +191,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t
/** /**
* @brief Set the Reverse Output data mode. * @brief Set the Reverse Output data mode.
* @param hcrc: CRC handle * @param hcrc CRC handle
* @param OutputReverseMode: Output Data inversion mode. * @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)

283
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp.c
View file

@ -54,6 +54,57 @@
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_CRYP_RegisterCallback() to register a user callback.
(#) Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input DMA transfer completion.
(+) OutCpltCallback : callback for output DMA transfer completion.
(+) CompCpltCallback : callback for computation completion.
(+) ErrorCallback : callback for error.
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input DMA transfer completion.
(+) OutCpltCallback : callback for output DMA transfer completion.
(+) CompCpltCallback : callback for computation completion.
(+) ErrorCallback : callback for error.
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
(#) By default, after the @ref HAL_CRYP_Init and if the state is HAL_CRYP_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_CRYP_InCpltCallback(), @ref HAL_CRYP_ErrorCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_CRYP_Init
and @ref HAL_CRYP_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init and @ref HAL_CRYP_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_CRYP_RegisterCallback before calling @ref HAL_CRYP_DeInit
or @ref HAL_¨CRYP_Init function.
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
@ -90,7 +141,7 @@
#ifdef HAL_CRYP_MODULE_ENABLED #ifdef HAL_CRYP_MODULE_ENABLED
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(AES)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
@ -259,6 +310,26 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Initialization */ /* Initialization */
/*================*/ /*================*/
/* Initialization start */ /* Initialization start */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
/* Reset Callback pointers in HAL_CRYP_STATE_RESET only */
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */
hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */
if(hcryp->MspInitCallback == NULL)
{
hcryp->MspInitCallback = HAL_CRYP_MspInit;
}
/* Init the low level hardware */
hcryp->MspInitCallback(hcryp);
}
#else
if(hcryp->State == HAL_CRYP_STATE_RESET) if(hcryp->State == HAL_CRYP_STATE_RESET)
{ {
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
@ -267,6 +338,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Init the low level hardware */ /* Init the low level hardware */
HAL_CRYP_MspInit(hcryp); HAL_CRYP_MspInit(hcryp);
} }
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
/* Change the CRYP state */ /* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY; hcryp->State = HAL_CRYP_STATE_BUSY;
@ -404,8 +476,18 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP Peripheral Clock */ /* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp); __HAL_CRYP_DISABLE(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
if(hcryp->MspDeInitCallback == NULL)
{
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
}
/* DeInit the low level hardware */
hcryp->MspDeInitCallback(hcryp);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp); HAL_CRYP_MspDeInit(hcryp);
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
/* Change the CRYP state */ /* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_RESET; hcryp->State = HAL_CRYP_STATE_RESET;
@ -1096,6 +1178,195 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
*/ */
} }
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User CRYP Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hcryp CRYP handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID
* @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID
* @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID
* @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hcryp);
if(HAL_CRYP_STATE_READY == hcryp->State)
{
switch (CallbackID)
{
case HAL_CRYP_INPUTCPLT_CB_ID :
hcryp->InCpltCallback = pCallback;
break;
case HAL_CRYP_OUTPUTCPLT_CB_ID :
hcryp->OutCpltCallback = pCallback;
break;
case HAL_CRYP_COMPCPLT_CB_ID :
hcryp->CompCpltCallback = pCallback;
break;
case HAL_CRYP_ERROR_CB_ID :
hcryp->ErrorCallback = pCallback;
break;
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = pCallback;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_CRYP_STATE_RESET == hcryp->State)
{
switch (CallbackID)
{
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = pCallback;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcryp);
return status;
}
/**
* @brief Unregister a CRYP Callback
* CRYP Callback is redirected to the weak (surcharged) predefined callback
* @param hcryp CRYP handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUTCPLT_CB_ID CRYP input DMA transfer completion Callback ID
* @arg @ref HAL_CRYP_OUTPUTCPLT_CB_ID CRYP output DMA transfer completion Callback ID
* @arg @ref HAL_CRYP_COMPCPLT_CB_ID CRYP computation completion Callback ID
* @arg @ref HAL_CRYP_ERROR_CB_ID CRYP error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID CRYP MspDeInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID CRYP MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hcryp);
if(HAL_CRYP_STATE_READY == hcryp->State)
{
switch (CallbackID)
{
case HAL_CRYP_INPUTCPLT_CB_ID :
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak (surcharged) input DMA transfer completion callback */
break;
case HAL_CRYP_OUTPUTCPLT_CB_ID :
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak (surcharged) output DMA transfer completion callback */
break;
case HAL_CRYP_COMPCPLT_CB_ID :
hcryp->CompCpltCallback = HAL_CRYPEx_ComputationCpltCallback; /* Legacy weak (surcharged) computation completion callback */
break;
case HAL_CRYP_ERROR_CB_ID :
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak (surcharged) error callback */
break;
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp DeInit */
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(HAL_CRYP_STATE_RESET == hcryp->State)
{
switch (CallbackID)
{
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hcryp);
return status;
}
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1148,7 +1419,11 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->ErrorCallback(hcryp);
#else
HAL_CRYP_ErrorCallback(hcryp); HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return; return;
} }
@ -1384,7 +1659,11 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return HAL_OK; return HAL_OK;
} }
@ -1448,7 +1727,7 @@ static HAL_StatusTypeDef CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
* @} * @}
*/ */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */ #endif /* HAL_CRYP_MODULE_ENABLED */

60
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_cryp_ex.c
View file

@ -41,7 +41,7 @@
#ifdef HAL_CRYP_MODULE_ENABLED #ifdef HAL_CRYP_MODULE_ENABLED
#if defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #if defined(AES)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
@ -1630,7 +1630,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI
hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
/* Call output data transfer complete callback */ /* Call output data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->OutCpltCallback(hcryp);
#else
HAL_CRYP_OutCpltCallback(hcryp); HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
else else
{ {
@ -1896,7 +1900,11 @@ void HAL_CRYPEx_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Output
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->ErrorCallback(hcryp);
#else
HAL_CRYP_ErrorCallback(hcryp); HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return ; return ;
} }
} }
@ -2121,7 +2129,11 @@ static void CRYP_Authentication_DMAInCplt(DMA_HandleTypeDef *hdma)
This allows to avoid the Wait on Flag within the IRQ handling. */ This allows to avoid the Wait on Flag within the IRQ handling. */
/* Call input data transfer complete callback */ /* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->InCpltCallback(hcryp);
#else
HAL_CRYP_InCpltCallback(hcryp); HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
/** /**
@ -2158,7 +2170,11 @@ static void CRYP_Authentication_DMAOutCplt(DMA_HandleTypeDef *hdma)
hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER; hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_OVER;
/* Call output data transfer complete callback */ /* Call output data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->OutCpltCallback(hcryp);
#else
HAL_CRYP_OutCpltCallback(hcryp); HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
/** /**
@ -2173,7 +2189,11 @@ static void CRYP_Authentication_DMAError(DMA_HandleTypeDef *hdma)
hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->State= HAL_CRYP_STATE_ERROR;
hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->ErrorCallback(hcryp);
#else
HAL_CRYP_ErrorCallback(hcryp); HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/* Clear Error Flag */ /* Clear Error Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
} }
@ -2224,7 +2244,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return HAL_OK; return HAL_OK;
} }
/*========================================*/ /*========================================*/
@ -2248,7 +2272,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return HAL_OK; return HAL_OK;
} }
@ -2432,7 +2460,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
return HAL_OK; return HAL_OK;
} }
@ -2483,7 +2515,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return HAL_OK; return HAL_OK;
} }
@ -2616,7 +2652,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
/* Call computation complete callback */ /* Call computation complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->CompCpltCallback(hcryp);
#else
HAL_CRYPEx_ComputationCpltCallback(hcryp); HAL_CRYPEx_ComputationCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
return HAL_OK; return HAL_OK;
} }
@ -2920,7 +2960,11 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
/* Call input data transfer complete callback */ /* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->InCpltCallback(hcryp);
#else
HAL_CRYP_InCpltCallback(hcryp); HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
/** /**
@ -2945,7 +2989,11 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
hcryp->State = HAL_CRYP_STATE_READY; hcryp->State = HAL_CRYP_STATE_READY;
/* Call output data transfer complete callback */ /* Call output data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->OutCpltCallback(hcryp);
#else
HAL_CRYP_OutCpltCallback(hcryp); HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
/** /**
@ -2959,7 +3007,11 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
hcryp->State= HAL_CRYP_STATE_ERROR; hcryp->State= HAL_CRYP_STATE_ERROR;
hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR; hcryp->ErrorCode |= HAL_CRYP_DMA_ERROR;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->ErrorCallback(hcryp);
#else
HAL_CRYP_ErrorCallback(hcryp); HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/* Clear Error Flag */ /* Clear Error Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
} }
@ -3038,7 +3090,11 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_
{ {
hcryp->State = HAL_CRYP_STATE_READY; hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp); __HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
hcryp->ErrorCallback(hcryp);
#else
HAL_CRYP_ErrorCallback(hcryp); HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
} }
/* Clear CCF Flag */ /* Clear CCF Flag */
@ -3129,7 +3185,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_
* @} * @}
*/ */
#endif /* defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L462xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ #endif /* AES */
#endif /* HAL_CRYP_MODULE_ENABLED */ #endif /* HAL_CRYP_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

344
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac.c
View file

@ -215,6 +215,64 @@
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
or @ref HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** DAC HAL driver macros list *** *** DAC HAL driver macros list ***
============================================= =============================================
[..] [..]
@ -339,11 +397,38 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
if(hdac->State == HAL_DAC_STATE_RESET) if(hdac->State == HAL_DAC_STATE_RESET)
{ {
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the DAC Callback settings */
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
if(hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
if(hdac->MspDeInitCallback == NULL)
{
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED; hdac->Lock = HAL_UNLOCKED;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */ /* Init the low level hardware */
HAL_DAC_MspInit(hdac); HAL_DAC_MspInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} }
/* Initialize the DAC state*/ /* Initialize the DAC state*/
@ -379,8 +464,18 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/* Change DAC state */ /* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY; hdac->State = HAL_DAC_STATE_BUSY;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
if(hdac->MspDeInitCallback == NULL)
{
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
}
/* DeInit the low level hardware */
hdac->MspDeInitCallback(hdac);
#else
/* DeInit the low level hardware */ /* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac); HAL_DAC_MspDeInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */ /* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE; hdac->ErrorCode = HAL_DAC_ERROR_NONE;
@ -879,7 +974,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Error callback */ /* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac); HAL_DAC_DMAUnderrunCallbackCh1(hdac);
#endif
} }
} }
#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
@ -887,7 +986,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx)
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{ {
/* Check underrun flag of DAC channel 1 */ /* Check underrun flag of DAC channel 2 */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{ {
/* Change DAC state to error state */ /* Change DAC state to error state */
@ -903,7 +1002,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Error callback */ /* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac); HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
#endif
} }
} }
#endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */
@ -1053,6 +1156,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* Returns the DAC channel data output register value */ /* Returns the DAC channel data output register value */
#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
/* Prevent unused argument(s) compilation warning if no assert_param check */
UNUSED(Channel);
return hdac->Instance->DOR1; return hdac->Instance->DOR1;
#endif /* STM32L451xx STM32L452xx STM32L462xx */ #endif /* STM32L451xx STM32L452xx STM32L462xx */
@ -1260,6 +1366,228 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
return HAL_OK; return HAL_OK;
} }
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
*
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
if(hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = pCallback;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
case HAL_DAC_MSP_INIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSP_DEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSP_INIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSP_DEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
* @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdac);
if(hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
case HAL_DAC_MSP_INIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSP_DEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
case HAL_DAC_ALL_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
hdac->MspInitCallback = HAL_DAC_MspInit;
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSP_INIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSP_DEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1326,7 +1654,11 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{ {
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvCpltCallbackCh1(hdac); HAL_DAC_ConvCpltCallbackCh1(hdac);
#endif
hdac->State= HAL_DAC_STATE_READY; hdac->State= HAL_DAC_STATE_READY;
} }
@ -1340,8 +1672,13 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{ {
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */ /* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvHalfCpltCallbackCh1(hdac); HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
#endif
} }
/** /**
@ -1357,7 +1694,11 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */ /* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA; hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh1(hdac);
#else
HAL_DAC_ErrorCallbackCh1(hdac); HAL_DAC_ErrorCallbackCh1(hdac);
#endif
hdac->State= HAL_DAC_STATE_READY; hdac->State= HAL_DAC_STATE_READY;
} }
@ -1368,6 +1709,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
#endif /* HAL_DAC_MODULE_ENABLED */ #endif /* HAL_DAC_MODULE_ENABLED */
/** /**
* @} * @}
*/ */

14
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dac_ex.c
View file

@ -594,7 +594,11 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{ {
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac); HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif
hdac->State= HAL_DAC_STATE_READY; hdac->State= HAL_DAC_STATE_READY;
} }
@ -608,8 +612,13 @@ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{ {
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */ /* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
#endif
} }
/** /**
@ -625,8 +634,11 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
/* Set DAC error code to DMA error */ /* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA; hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh2(hdac);
#else
HAL_DACEx_ErrorCallbackCh2(hdac); HAL_DACEx_ErrorCallbackCh2(hdac);
#endif
hdac->State= HAL_DAC_STATE_READY; hdac->State= HAL_DAC_STATE_READY;
} }

428
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dcmi.c
View file

@ -15,11 +15,11 @@
##### How to use this driver ##### ##### How to use this driver #####
============================================================================== ==============================================================================
[..] [..]
The sequence below describes how to use this driver to capture an image The sequence below describes how to use this driver to capture images
from a camera module connected to the DCMI Interface. from a camera module connected to the DCMI Interface.
This sequence does not take into account the configuration of the This sequence does not take into account the configuration of the
camera module, which should be made before configuring and enabling camera module, which should be made before configuring and enabling
the DCMI. the DCMI to capture images.
(#) Program the required configuration through the following parameters: (#) Program the required configuration through the following parameters:
horizontal and vertical polarity, pixel clock polarity, capture rate, horizontal and vertical polarity, pixel clock polarity, capture rate,
@ -91,8 +91,57 @@
(+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
and that the interruption is enabled at the same time.
*** Callback registration ***
=============================
The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback.
Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks:
(+) FrameEventCallback : DCMI Frame Event.
(+) VsyncEventCallback : DCMI Vsync Event.
(+) LineEventCallback : DCMI Line Event.
(+) ErrorCallback : DCMI error.
(+) MspInitCallback : DCMI MspInit.
(+) MspDeInitCallback : DCMI MspDeInit.
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
This function allows to reset following callbacks:
(+) FrameEventCallback : DCMI Frame Event.
(+) VsyncEventCallback : DCMI Vsync Event.
(+) LineEventCallback : DCMI Line Event.
(+) ErrorCallback : DCMI error.
(+) MspInitCallback : DCMI MspInit.
(+) MspDeInitCallback : DCMI MspDeInit.
By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init
and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit
or @ref HAL_DCMI_Init function.
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
@ -129,9 +178,7 @@
#include "stm32l4xx_hal.h" #include "stm32l4xx_hal.h"
#ifdef HAL_DCMI_MODULE_ENABLED #ifdef HAL_DCMI_MODULE_ENABLED
#if defined (DCMI)
#if defined(STM32L496xx) || defined(STM32L4A6xx) || \
defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
@ -150,24 +197,7 @@
/** @defgroup DCMI_Stop_TimeOut DCMI Stop TimeOut /** @defgroup DCMI_Stop_TimeOut DCMI Stop TimeOut
* @{ * @{
*/ */
#define DCMI_TIMEOUT_STOP ((uint32_t)1000) /*!< 1s */ #define DCMI_TIMEOUT_STOP ((uint32_t)1000U) /*!< 1s */
/**
* @}
*/
/** @defgroup DCMI_Shifts DCMI Shifts
* @{
*/
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
#define DCMI_POSITION_ESUR_LSU (uint32_t)POSITION_VAL(DCMI_ESUR_LSU) /*!< Required left shift to set line start delimiter unmask */
#define DCMI_POSITION_ESUR_LEU (uint32_t)POSITION_VAL(DCMI_ESUR_LEU) /*!< Required left shift to set line end delimiter unmask */
#define DCMI_POSITION_ESUR_FEU (uint32_t)POSITION_VAL(DCMI_ESUR_FEU) /*!< Required left shift to set frame end delimiter unmask */
/** /**
* @} * @}
*/ */
@ -218,7 +248,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize);
/** /**
* @brief Initialize the DCMI according to the specified * @brief Initialize the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle. * parameters in the DCMI_InitTypeDef and create the associated handle.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @note By default, all interruptions are enabled (line end, frame end, overrun, * @note By default, all interruptions are enabled (line end, frame end, overrun,
* VSYNC and embedded synchronization error interrupts). * VSYNC and embedded synchronization error interrupts).
@ -251,8 +281,25 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{ {
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hdcmi->Lock = HAL_UNLOCKED; hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
/* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
if(hdcmi->MspInitCallback == NULL)
{
/* Legacy weak MspInit Callback */
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
}
/* Initialize the low level hardware (MSP) */
hdcmi->MspInitCallback(hdcmi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspInit(hdcmi); HAL_DCMI_MspInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
} }
/* Change the DCMI state */ /* Change the DCMI state */
@ -284,9 +331,9 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{ {
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SynchroCode.FrameStartCode) |\ hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SynchroCode.FrameStartCode) |\
((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\ ((uint32_t)hdcmi->Init.SynchroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\ ((uint32_t)hdcmi->Init.SynchroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); ((uint32_t)hdcmi->Init.SynchroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
} }
/* By default, enable all interrupts. The user may disable the unwanted ones /* By default, enable all interrupts. The user may disable the unwanted ones
@ -311,7 +358,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief De-initialize the DCMI peripheral, reset control registers to * @brief De-initialize the DCMI peripheral, reset control registers to
* their default values. * their default values.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
@ -328,12 +375,21 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
} }
} }
/* DeInit the DCMI low level hardware */
HAL_DCMI_MspDeInit(hdcmi);
/* Reset DCMI control register */ /* Reset DCMI control register */
hdcmi->Instance->CR = 0; hdcmi->Instance->CR = 0;
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
if(hdcmi->MspDeInitCallback == NULL)
{
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
}
/* De-Initialize the low level hardware (MSP) */
hdcmi->MspDeInitCallback(hdcmi);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspDeInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
/* Update error code */ /* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@ -348,7 +404,7 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Initialize the DCMI MSP. * @brief Initialize the DCMI MSP.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -364,7 +420,7 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
/** /**
* @brief De-initialize the DCMI MSP. * @brief De-initialize the DCMI MSP.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -408,11 +464,11 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
/** /**
* @brief Enable DCMI capture in DMA mode. * @brief Enable DCMI capture in DMA mode.
* @param hdcmi: Pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi Pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. * @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory buffer address. * @param pData The destination memory buffer address.
* @param Length: The length of capture to be transferred (in 32-bit words). * @param Length The length of capture to be transferred (in 32-bit words).
* @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length), * @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length),
* the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA() * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA()
* initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each
@ -450,6 +506,9 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Set the DMA error callback */ /* Set the DMA error callback */
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
/* Set the dma abort callback */
hdcmi->DMA_Handle->XferAbortCallback = NULL;
if(Length <= 0xFFFF) if(Length <= 0xFFFF)
{ {
hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */ hdcmi->XferCount = 0; /* Mark as direct transfer from DCMI_DR register to final destination buffer */
@ -537,13 +596,14 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/** /**
* @brief Disable DCMI capture in DMA mode. * @brief Disable DCMI capture in DMA mode.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{ {
uint32_t tickstart = 0; uint32_t tickstart = 0;
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */ /* Process locked */
__HAL_LOCK(hdcmi); __HAL_LOCK(hdcmi);
@ -565,13 +625,8 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Update error code */ /* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
/* Change DCMI state */ status = HAL_TIMEOUT;
hdcmi->State = HAL_DCMI_STATE_READY; break;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_TIMEOUT;
} }
} }
@ -588,12 +643,12 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
__HAL_UNLOCK(hdcmi); __HAL_UNLOCK(hdcmi);
/* Return function status */ /* Return function status */
return HAL_OK; return status;
} }
/** /**
* @brief Suspend DCMI capture. * @brief Suspend DCMI capture.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
@ -643,7 +698,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
/** /**
* @brief Resume DCMI capture. * @brief Resume DCMI capture.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
@ -669,7 +724,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
/** /**
* @brief Handle DCMI interrupt request. * @brief Handle DCMI interrupt request.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI. * the configuration information for the DCMI.
* @retval None * @retval None
*/ */
@ -707,9 +762,6 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
/* Abort the DMA Transfer */ /* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle); HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
/* Error Callback */
HAL_DCMI_ErrorCallback(hdcmi);
} }
/* Line Interrupt management ************************************************/ /* Line Interrupt management ************************************************/
@ -718,8 +770,13 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
/* Clear the Line interrupt flag */ /* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */ /* Line interrupt Event Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI line event callback*/
hdcmi->LineEventCallback(hdcmi);
#else
HAL_DCMI_LineEventCallback(hdcmi); HAL_DCMI_LineEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
/* VSYNC interrupt management ***********************************************/ /* VSYNC interrupt management ***********************************************/
@ -728,8 +785,13 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
/* Clear the VSYNC flag */ /* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */ /* VSYNC Event Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI vsync event callback*/
hdcmi->VsyncEventCallback(hdcmi);
#else
HAL_DCMI_VsyncEventCallback(hdcmi); HAL_DCMI_VsyncEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
/* End of Frame interrupt management ****************************************/ /* End of Frame interrupt management ****************************************/
@ -746,14 +808,19 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
/* Clear the End of Frame flag */ /* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* End of Frame Callback */ /* Frame Event Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI frame event callback*/
hdcmi->FrameEventCallback(hdcmi);
#else
HAL_DCMI_FrameEventCallback(hdcmi); HAL_DCMI_FrameEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
} }
/** /**
* @brief Error DCMI callback. * @brief Error DCMI callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -769,7 +836,7 @@ __weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Line Event callback. * @brief Line Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -785,7 +852,7 @@ __weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief VSYNC Event callback. * @brief VSYNC Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -801,7 +868,7 @@ __weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Frame Event callback. * @brief Frame Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval None * @retval None
*/ */
@ -838,13 +905,13 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Configure the DCMI crop window coordinates. * @brief Configure the DCMI crop window coordinates.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @param X0: DCMI window crop window X offset (number of pixels clocks to count before the capture). * @param X0 DCMI window crop window X offset (number of pixels clocks to count before the capture).
* @param Y0: DCMI window crop window Y offset (image capture starts with this line number, previous * @param Y0 DCMI window crop window Y offset (image capture starts with this line number, previous
* line data are ignored). * line data are ignored).
* @param XSize: DCMI crop window horizontal size (in number of pixels per line). * @param XSize DCMI crop window horizontal size (in number of pixels per line).
* @param YSize: DCMI crop window vertical size (in lines count). * @param YSize DCMI crop window vertical size (in lines count).
* @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line, * @note For all the parameters, the actual value is the input data + 1 (e.g. YSize = 0x0 means 1 line,
* YSize = 0x1 means 2 lines, ...) * YSize = 0x1 means 2 lines, ...)
* @retval HAL status * @retval HAL status
@ -864,8 +931,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
hdcmi->State = HAL_DCMI_STATE_BUSY; hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configure CROP */ /* Configure CROP */
MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE))); MODIFY_REG(hdcmi->Instance->CWSIZER, (DCMI_CWSIZE_VLINE|DCMI_CWSIZE_CAPCNT), (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos)));
MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST))); MODIFY_REG(hdcmi->Instance->CWSTRTR, (DCMI_CWSTRT_VST|DCMI_CWSTRT_HOFFCNT), (X0 | (Y0 << DCMI_CWSTRT_VST_Pos)));
/* Initialize the DCMI state*/ /* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY; hdcmi->State = HAL_DCMI_STATE_READY;
@ -878,7 +945,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
/** /**
* @brief Disable the crop feature. * @brief Disable the crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
@ -904,7 +971,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Enable the crop feature. * @brief Enable the crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL status * @retval HAL status
*/ */
@ -930,9 +997,9 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Set embedded synchronization delimiters unmasks. * @brief Set embedded synchronization delimiters unmasks.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @param SyncUnmask: pointer to a DCMI_SyncUnmaskTypeDef structure that contains * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
* the embedded synchronization delimiters unmasks. * the embedded synchronization delimiters unmasks.
* @retval HAL status * @retval HAL status
*/ */
@ -946,9 +1013,9 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn
/* Write DCMI embedded synchronization unmask register */ /* Write DCMI embedded synchronization unmask register */
hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\ hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) |\
((uint32_t)SyncUnmask->LineStartUnmask << DCMI_POSITION_ESUR_LSU)|\ ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos)|\
((uint32_t)SyncUnmask->LineEndUnmask << DCMI_POSITION_ESUR_LEU)|\ ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos)|\
((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_POSITION_ESUR_FEU)); ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
/* Change the DCMI state*/ /* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY; hdcmi->State = HAL_DCMI_STATE_READY;
@ -984,7 +1051,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_Syn
/** /**
* @brief Return the DCMI state. * @brief Return the DCMI state.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval HAL state * @retval HAL state
*/ */
@ -995,7 +1062,7 @@ HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief Return the DCMI error code. * @brief Return the DCMI error code.
* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI. * the configuration information for DCMI.
* @retval DCMI Error Code * @retval DCMI Error Code
*/ */
@ -1008,6 +1075,171 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
* @} * @}
*/ */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
* @brief DCMI Callback registering
* @param hdcmi dcmi handle
* @param CallbackID dcmi Callback ID
* @param pCallback pointer to dcmi Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if(pCallback == NULL)
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if(hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief DCMI Callback Unregistering
* @param hdcmi dcmi handle
* @param CallbackID dcmi Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if(hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -1019,7 +1251,7 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
/** /**
* @brief DMA conversion complete callback. * @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @note When the size of the frame being captured by the DCMI peripheral is * @note When the size of the frame being captured by the DCMI peripheral is
* larger than 0xFFFF (DMA maximum transfer length), this API initiates * larger than 0xFFFF (DMA maximum transfer length), this API initiates
@ -1070,8 +1302,13 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdcmi); __HAL_UNLOCK(hdcmi);
/* Error Callback */ /* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi); HAL_DCMI_ErrorCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
} }
else else
@ -1097,8 +1334,13 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
__HAL_UNLOCK(hdcmi); __HAL_UNLOCK(hdcmi);
} }
/* FRAME Callback */ /* Frame Event Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI frame event callback*/
hdcmi->FrameEventCallback(hdcmi);
#else
HAL_DCMI_FrameEventCallback(hdcmi); HAL_DCMI_FrameEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
} }
} }
@ -1107,7 +1349,7 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
/** /**
* @brief DMA Half Transfer complete callback. * @brief DMA Half Transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @note When the size of the frame being captured by the DCMI peripheral is * @note When the size of the frame being captured by the DCMI peripheral is
* larger than 0xFFFF (DMA maximum transfer length), this API initiates * larger than 0xFFFF (DMA maximum transfer length), this API initiates
@ -1156,15 +1398,20 @@ static void DCMI_DMAHalfXferCplt(DMA_HandleTypeDef *hdma)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdcmi); __HAL_UNLOCK(hdcmi);
/* Error Callback */ /* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi); HAL_DCMI_ErrorCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
} }
} }
/** /**
* @brief DMA error callback * @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module. * the configuration information for the specified DMA module.
* @retval None * @retval None
*/ */
@ -1178,8 +1425,13 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
/* Change DCMI state */ /* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY; hdcmi->State = HAL_DCMI_STATE_READY;
/* Error Callback */ /* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi); HAL_DCMI_ErrorCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
} }
/** /**
@ -1192,7 +1444,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
* buffer size and is as high as possible. The API implements a sub-optimum solution for * buffer size and is as high as possible. The API implements a sub-optimum solution for
* complexity's sake. * complexity's sake.
* @note InputSize MUST be even. * @note InputSize MUST be even.
* @param InputSize: full buffer size (in 32-bit words) * @param InputSize full buffer size (in 32-bit words)
* @retval Transfer size (in 32-bit words) * @retval Transfer size (in 32-bit words)
*/ */
static uint32_t DCMI_TransferSize(uint32_t InputSize) static uint32_t DCMI_TransferSize(uint32_t InputSize)
@ -1260,9 +1512,7 @@ static uint32_t DCMI_TransferSize(uint32_t InputSize)
* @} * @}
*/ */
#endif /* STM32L496xx || STM32L4A6xx || */ #endif /* DCMI */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#endif /* HAL_DCMI_MODULE_ENABLED */ #endif /* HAL_DCMI_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

760
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dfsdm.c
View file

File diff suppressed because it is too large Load diff

154
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma.c
View file

@ -66,7 +66,7 @@
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
[..] [..]
(@) You can refer to the DMA HAL driver header file for more useful macros (@) You can refer to the DMA HAL driver header file for more useful macros
@ -162,13 +162,13 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
/** /**
* @brief Initialize the DMA according to the specified * @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle. * parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{ {
uint32_t tmp = 0; uint32_t tmp;
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if(hdma == NULL) if(hdma == NULL)
@ -241,7 +241,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{ {
/* Initialize parameters for DMAMUX request generator : /* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -271,18 +271,18 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
if (DMA1 == hdma->DmaBaseAddress) if (DMA1 == hdma->DmaBaseAddress)
{ {
/* Reset request selection for DMA1 Channelx */ /* Reset request selection for DMA1 Channelx */
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA1 Channelx */ /* Configure request selection for DMA1 Channelx */
DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
} }
else /* DMA2 */ else /* DMA2 */
{ {
/* Reset request selection for DMA2 Channelx */ /* Reset request selection for DMA2 Channelx */
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
/* Configure request selection for DMA2 Channelx */ /* Configure request selection for DMA2 Channelx */
DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU));
} }
} }
@ -290,12 +290,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
/* STM32L496xx || STM32L4A6xx */ /* STM32L496xx || STM32L4A6xx */
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialise the error code */ /* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -310,7 +304,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/** /**
* @brief DeInitialize the DMA peripheral. * @brief DeInitialize the DMA peripheral.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -347,7 +341,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->Instance->CCR = 0; hdma->Instance->CCR = 0;
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
#if !defined (DMAMUX1) #if !defined (DMAMUX1)
@ -355,12 +349,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
if (DMA1 == hdma->DmaBaseAddress) if (DMA1 == hdma->DmaBaseAddress)
{ {
/* DMA1 */ /* DMA1 */
DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
} }
else else
{ {
/* DMA2 */ /* DMA2 */
DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU));
} }
#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */
/* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */
@ -380,7 +374,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Reset Request generator parameters if any */ /* Reset Request generator parameters if any */
if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
{ {
/* Initialize parameters for DMAMUX request generator : /* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
@ -400,6 +394,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialise the error code */ /* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -437,11 +437,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/** /**
* @brief Start the DMA Transfer. * @brief Start the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -480,11 +480,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/** /**
* @brief Start the DMA Transfer with interrupt enabled. * @brief Start the DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/** /**
* @brief Abort the DMA Transfer. * @brief Abort the DMA Transfer.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -582,7 +582,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
#if defined(DMAMUX1) #if defined(DMAMUX1)
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
@ -611,7 +611,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/** /**
* @brief Aborts the DMA Transfer in Interrupt mode. * @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
@ -639,7 +639,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
/* Clear the DMAMUX synchro overrun flag */ /* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
#else #else
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
/* Change the DMA state */ /* Change the DMA state */
@ -676,16 +676,16 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/** /**
* @brief Polling for transfer complete. * @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CompleteLevel: Specifies the DMA level complete. * @param CompleteLevel Specifies the DMA level complete.
* @param Timeout: Timeout duration. * @param Timeout Timeout duration.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
{ {
uint32_t temp; uint32_t temp;
uint32_t tickstart = 0; uint32_t tickstart;
if(HAL_DMA_STATE_BUSY != hdma->State) if(HAL_DMA_STATE_BUSY != hdma->State)
{ {
@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
} }
/* Polling mode not supported in circular mode */ /* Polling mode not supported in circular mode */
if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
{ {
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR; return HAL_ERROR;
@ -706,25 +706,25 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
if (HAL_DMA_FULL_TRANSFER == CompleteLevel) if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{ {
/* Transfer Complete flag */ /* Transfer Complete flag */
temp = DMA_FLAG_TC1 << hdma->ChannelIndex; temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU);
} }
else else
{ {
/* Half Transfer Complete flag */ /* Half Transfer Complete flag */
temp = DMA_FLAG_HT1 << hdma->ChannelIndex; temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU);
} }
/* Get tick */ /* Get tick */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
while(RESET == (hdma->DmaBaseAddress->ISR & temp)) while(0U == (hdma->DmaBaseAddress->ISR & temp))
{ {
if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU)))))
{ {
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE; hdma->ErrorCode = HAL_DMA_ERROR_TE;
@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Check for the Timeout */ /* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY) if(Timeout != HAL_MAX_DELAY)
{ {
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{ {
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
@ -788,7 +788,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
if(HAL_DMA_FULL_TRANSFER == CompleteLevel) if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{ {
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU));
/* The selected Channelx EN bit is cleared (DMA is disabled and /* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */ all transfers are complete) */
@ -797,7 +797,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
else else
{ {
/* Clear the half transfer complete flag */ /* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU));
} }
/* Process unlocked */ /* Process unlocked */
@ -808,7 +808,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/** /**
* @brief Handle DMA interrupt request. * @brief Handle DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval None * @retval None
*/ */
@ -818,16 +818,16 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
uint32_t source_it = hdma->Instance->CCR; uint32_t source_it = hdma->Instance->CCR;
/* Half Transfer Complete Interrupt management ******************************/ /* Half Transfer Complete Interrupt management ******************************/
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT)))
{ {
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the half transfer interrupt */ /* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
} }
/* Clear the half transfer complete flag */ /* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU);
/* DMA peripheral state is not updated in Half Transfer */ /* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */ /* but in Transfer Complete case */
@ -840,9 +840,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
} }
/* Transfer Complete Interrupt management ***********************************/ /* Transfer Complete Interrupt management ***********************************/
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
{ {
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
/* Disable the transfer complete and error interrupt */ /* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
@ -851,7 +851,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
} }
/* Clear the transfer complete flag */ /* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU));
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
@ -864,7 +864,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
} }
/* Transfer Error Interrupt management **************************************/ /* Transfer Error Interrupt management **************************************/
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE)))
{ {
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
@ -872,7 +872,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE; hdma->ErrorCode = HAL_DMA_ERROR_TE;
@ -889,16 +889,20 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
hdma->XferErrorCallback(hdma); hdma->XferErrorCallback(hdma);
} }
} }
else
{
/* Nothing To Do */
}
return; return;
} }
/** /**
* @brief Register callbacks * @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to * @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter. * a DMA_HandleTypeDef structure as parameter.
* @retval HAL status * @retval HAL status
*/ */
@ -947,9 +951,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
/** /**
* @brief UnRegister callbacks * @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status * @retval HAL status
*/ */
@ -1027,7 +1031,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
/** /**
* @brief Return the DMA hande state. * @brief Return the DMA hande state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL state * @retval HAL state
*/ */
@ -1062,11 +1066,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
/** /**
* @brief Sets the DMA Transfer parameter. * @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address * @param SrcAddress The source memory Buffer address
* @param DstAddress: The destination memory Buffer address * @param DstAddress The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status * @retval HAL status
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@ -1083,12 +1087,12 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
#endif #endif
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU));
/* Configure DMA Channel data length */ /* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength; hdma->Instance->CNDTR = DataLength;
/* Peripheral to Memory */ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{ {
/* Configure DMA Channel destination address */ /* Configure DMA Channel destination address */
@ -1097,7 +1101,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress; hdma->Instance->CMAR = SrcAddress;
} }
/* Memory to Peripheral */ /* Peripheral to Memory */
else else
{ {
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
@ -1112,13 +1116,13 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/** /**
* @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval None * @retval None
*/ */
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{ {
uint32_t channel_number = 0; uint32_t channel_number;
DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
/* check if instance is not outside the DMA channel range */ /* check if instance is not outside the DMA channel range */
@ -1132,15 +1136,15 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
/* DMA2 */ /* DMA2 */
DMAMUX1_ChannelBase = DMAMUX1_Channel7; DMAMUX1_ChannelBase = DMAMUX1_Channel7;
} }
channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
hdma->DMAmuxChannelStatusMask = 1U << channel_number; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
} }
/** /**
* @brief Updates the DMA handle with the DMAMUX request generator params * @brief Updates the DMA handle with the DMAMUX request generator params
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval None * @retval None
*/ */
@ -1154,7 +1158,9 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
} }
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */

753
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma2d.c
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2
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dma_ex.c
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@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
/* Set the request generator new parameters */ /* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
pRequestGeneratorConfig->Polarity; pRequestGeneratorConfig->Polarity;
/* Process UnLocked */ /* Process UnLocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);

631
ext/hal/st/stm32cube/stm32l4xx/drivers/src/stm32l4xx_hal_dsi.c
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