driver: crypto: add crypto driver for rts5912
Add crypto driver for Realtek rts5912 Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
This commit is contained in:
Lin Yu-Cheng
Fabio Baltieri
parent
e571f8bab4
commit
b2e13bd6c3
8 changed files with 496 additions and 0 deletions
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@ -15,4 +15,5 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA_V2 crypto_it8xxx2_sha_v2.
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP crypto_mcux_dcp.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP crypto_mcux_dcp.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_SI32 crypto_si32.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_SI32 crypto_si32.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_CC23X0 crypto_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_CC23X0 crypto_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_RTS5912_SHA crypto_rts5912_sha.c)
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zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
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zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
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@ -59,5 +59,6 @@ source "drivers/crypto/Kconfig.mcux_dcp"
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source "drivers/crypto/Kconfig.si32"
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source "drivers/crypto/Kconfig.si32"
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source "drivers/crypto/Kconfig.smartbond"
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source "drivers/crypto/Kconfig.smartbond"
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source "drivers/crypto/Kconfig.cc23x0"
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source "drivers/crypto/Kconfig.cc23x0"
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source "drivers/crypto/Kconfig.rts5912"
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endif # CRYPTO
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endif # CRYPTO
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11
drivers/crypto/Kconfig.rts5912
Normal file
11
drivers/crypto/Kconfig.rts5912
Normal file
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
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#
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config CRYPTO_RTS5912_SHA
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bool "Realtek embedded controller (EC) SHA2 driver"
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depends on DT_HAS_REALTEK_RTS5912_SHA_ENABLED
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default y
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help
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Enable SHA driver.
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29
drivers/crypto/crypto_rts5912_priv.h
Normal file
29
drivers/crypto/crypto_rts5912_priv.h
Normal file
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@ -0,0 +1,29 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
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*
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*/
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#ifndef ZEPHYR_DRIVERS_CRYPTO_CRYPTO_RTS5912_PRIV_H_
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#define ZEPHYR_DRIVERS_CRYPTO_CRYPTO_RTS5912_PRIV_H_
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struct rts5912_sha256_context {
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uint32_t total[2];
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uint32_t state[8];
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uint8_t buffer[64];
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uint8_t sha2_data_in_sram[1024];
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struct k_mutex crypto_rts5912_in_use;
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bool in_use;
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bool is224;
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};
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struct rts5912_sha_config {
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volatile struct sha2_type *cfg_sha2_regs;
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volatile struct sha2dma_type *cfg_sha2dma_regs;
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};
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const uint32_t rts5912_sha224_digest[] = {0xC1059ED8, 0x367CD507, 0x3070DD17, 0xF70E5939,
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0xFFC00B31, 0x68581511, 0x64F98FA7, 0xBEFA4FA4};
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#endif /* ZEPHYR_DRIVERS_CRYPTO_CRYPTO_RTS5912_PRIV_H_ */
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351
drivers/crypto/crypto_rts5912_sha.c
Normal file
351
drivers/crypto/crypto_rts5912_sha.c
Normal file
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@ -0,0 +1,351 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
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*
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*/
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#define DT_DRV_COMPAT realtek_rts5912_sha
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#include <errno.h>
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#include <string.h>
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#include <zephyr/init.h>
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#include <zephyr/crypto/crypto.h>
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(sha256_hw_rtk, CONFIG_CRYPTO_LOG_LEVEL);
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"only one realtek,rts5912-sha compatible node can be supported");
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#include "reg/reg_crypto.h"
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#include "crypto_rts5912_priv.h"
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#define RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM (0x1FFUL)
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#define RTS5912_SHA2DMA_BLOCK_SIZE (64)
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#define RTS5912_SHA2DMA_BLOCK_SHIFT (6)
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#define RTS5912_SHA2DMA_8Byte_SHIFT (3)
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#define RTS5912_SHA2DMA_DST_WIDTH (0x3)
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#define RTS5912_SHA2DMA_SRC_WIDTH (0x3)
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#define RTS5912_SHA2DMA_HIGH_LEVEL_MSK (0xFFFF0000)
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#define RTS5912_SHA2_BLOCK_EXTEND_CHECK (56)
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#define RTS5912_MAXIMUM_CRYPTO_POLLING_TIME_US (50 * USEC_PER_MSEC)
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#define INT_COMPLETE_MASK \
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(SHA2DMA_INTSTS_TFR_COMPLETE_Msk | SHA2DMA_INTSTS_BLK_COMPLETE_Msk | \
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SHA2DMA_INTSTS_SCR_COMPLETE_Msk | SHA2DMA_INTSTS_DST_COMPLETE_Msk | \
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SHA2DMA_INTSTS_BUS_COMPLETE_Msk)
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static void rts5912_sha256_start(const struct device *dev)
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{
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const struct rts5912_sha_config *cfg = dev->config;
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volatile struct sha2_type *sha2_regs = (volatile struct sha2_type *)cfg->cfg_sha2_regs;
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volatile struct sha2dma_type *sha2dma_regs =
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(volatile struct sha2dma_type *)cfg->cfg_sha2dma_regs;
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struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
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if (rts5912_sha256_ctx->is224) {
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sha2_regs->ctrl = SHA2_CTRL_BYTEINV_Msk | SHA2_CTRL_ICGEN_Msk;
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for (uint32_t i = 0; i < 8; i++) {
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sha2_regs->digest[i << 1] = rts5912_sha224_digest[i];
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sha2_regs->digest[(i << 1) + 1] = 0x0;
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}
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} else {
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sha2_regs->ctrl = SHA2_CTRL_RST_Msk | SHA2_CTRL_BYTEINV_Msk | SHA2_CTRL_ICGEN_Msk;
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}
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sha2dma_regs->dma_enable = SHA2DMA_DMA_ENABLE_Msk;
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sha2dma_regs->config = 0x0;
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sha2dma_regs->dar = 0x0;
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sha2dma_regs->ctrl_low = (sha2dma_regs->ctrl_low & RTS5912_SHA2DMA_HIGH_LEVEL_MSK) |
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(SHA2DMA_CTRL_INT_EN_Msk |
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(RTS5912_SHA2DMA_DST_WIDTH << SHA2DMA_CTRL_DST_WIDTH_Pos) |
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(RTS5912_SHA2DMA_SRC_WIDTH << SHA2DMA_CTRL_SRC_WIDTH_Pos) |
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(0x2 << SHA2DMA_CTRL_SRC_BURST_Pos));
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sha2dma_regs->msk_transfer = (sha2dma_regs->msk_transfer & RTS5912_SHA2DMA_HIGH_LEVEL_MSK) |
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SHA2DMA_MSKTFR_INT_EN_Msk | SHA2DMA_MSKTFR_INT_WRITE_EN_Msk;
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sha2dma_regs->msk_block = 0x0;
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}
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static int rts5912_sha256_process(const struct device *dev, uint8_t *input, size_t blk_size)
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{
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const struct rts5912_sha_config *cfg = dev->config;
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volatile struct sha2_type *sha2_regs = (volatile struct sha2_type *)cfg->cfg_sha2_regs;
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volatile struct sha2dma_type *sha2dma_regs =
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(volatile struct sha2dma_type *)cfg->cfg_sha2dma_regs;
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struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
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uint32_t idx = 0;
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for (; blk_size > 0; blk_size -= RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM) {
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sha2dma_regs->sar = (uint32_t)(&(input[idx]));
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if (blk_size <= RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM) {
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sha2dma_regs->ctrl_high = blk_size << RTS5912_SHA2DMA_8Byte_SHIFT;
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} else {
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sha2dma_regs->ctrl_high = RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM
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<< RTS5912_SHA2DMA_8Byte_SHIFT;
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}
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sha2dma_regs->channel_enable = SHA2DMA_CHEN_EN_Msk | SHA2DMA_CHEN_WRITE_EN_Msk;
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uint32_t _wf_cycle_count =
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k_us_to_cyc_ceil32(RTS5912_MAXIMUM_CRYPTO_POLLING_TIME_US);
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uint32_t _wf_start = k_cycle_get_32();
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while (!((sha2dma_regs->interrupt_status & INT_COMPLETE_MASK) != 0) &&
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(_wf_cycle_count > (k_cycle_get_32() - _wf_start))) {
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k_msleep(1);
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Z_SPIN_DELAY(10);
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}
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if (_wf_cycle_count < (k_cycle_get_32() - _wf_start)) {
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LOG_ERR("SHA2DMA reach timeout and breach");
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return -EIO;
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}
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if (sha2dma_regs->interrupt_status & SHA2DMA_INTSTS_BUS_COMPLETE_Msk) {
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return -EIO;
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}
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sha2dma_regs->clear_transfer = SHA2DMA_INTCLR_CLRTFR_Msk;
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idx += RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM << RTS5912_SHA2DMA_BLOCK_SHIFT;
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if (blk_size <= RTS5912_SHA2DMA_MAXIMUM_BLOCK_NUM) {
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break;
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}
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}
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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for (uint32_t i = 0; i < 8; i++) {
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rts5912_sha256_ctx->state[i] = sha2_regs->digest[i << 1];
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}
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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return 0;
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}
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static int rts5912_sha256_update(const struct device *dev, uint8_t *input, size_t len)
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{
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struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
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uint32_t remain, fill, blk_size = 0, ret_val = 0;
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remain = rts5912_sha256_ctx->total[0] & (RTS5912_SHA2DMA_BLOCK_SIZE - 1);
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fill = RTS5912_SHA2DMA_BLOCK_SIZE - remain;
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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rts5912_sha256_ctx->total[0] += len;
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if (rts5912_sha256_ctx->total[0] < len) {
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rts5912_sha256_ctx->total[1]++;
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}
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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if ((len >= fill) && (remain != 0)) {
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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memcpy((void *)(&(rts5912_sha256_ctx->buffer[remain])), input, fill);
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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ret_val = rts5912_sha256_process(dev, (&(rts5912_sha256_ctx->buffer[0])), 0x1);
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if (ret_val != 0) {
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return ret_val;
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}
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input += fill;
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len -= fill;
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remain = 0;
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}
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while (len >= RTS5912_SHA2DMA_BLOCK_SIZE) {
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blk_size = len >> RTS5912_SHA2DMA_BLOCK_SHIFT;
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ret_val = rts5912_sha256_process(dev, input, blk_size);
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if (ret_val != 0) {
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return ret_val;
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}
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input += (len & ~(RTS5912_SHA2DMA_BLOCK_SIZE - 1));
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len &= (RTS5912_SHA2DMA_BLOCK_SIZE - 1);
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}
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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if (len > 0) {
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memcpy((void *)(&(rts5912_sha256_ctx->buffer[remain])), input, len);
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}
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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return ret_val;
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}
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static int rts5912_sha256_finish(const struct device *dev, uint8_t *output)
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{
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struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
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uint32_t remain, be_high, be_low, ret_val = 0;
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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remain = rts5912_sha256_ctx->total[0] & (RTS5912_SHA2DMA_BLOCK_SIZE - 1);
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rts5912_sha256_ctx->buffer[remain++] = 0x80U;
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if (remain <= RTS5912_SHA2_BLOCK_EXTEND_CHECK) {
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memset((void *)(&(rts5912_sha256_ctx->buffer[remain])), 0x0,
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RTS5912_SHA2_BLOCK_EXTEND_CHECK - remain);
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} else {
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memset((void *)(&(rts5912_sha256_ctx->buffer[remain])), 0x0,
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RTS5912_SHA2DMA_BLOCK_SIZE - remain);
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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ret_val = rts5912_sha256_process(dev, (uint8_t *)(&(rts5912_sha256_ctx->buffer[0])),
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0x1);
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if (ret_val != 0) {
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return ret_val;
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}
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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memset((void *)(&(rts5912_sha256_ctx->buffer[0])), 0x0,
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RTS5912_SHA2_BLOCK_EXTEND_CHECK);
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}
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be_high = (rts5912_sha256_ctx->total[0] >> (32 - RTS5912_SHA2DMA_8Byte_SHIFT)) |
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(rts5912_sha256_ctx->total[1] << RTS5912_SHA2DMA_8Byte_SHIFT);
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be_low = rts5912_sha256_ctx->total[0] << RTS5912_SHA2DMA_8Byte_SHIFT;
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*(uint32_t *)(&(rts5912_sha256_ctx->buffer[56])) = sys_cpu_to_be32(be_high);
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*(uint32_t *)(&(rts5912_sha256_ctx->buffer[60])) = sys_cpu_to_be32(be_low);
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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ret_val = rts5912_sha256_process(dev, (uint8_t *)(&(rts5912_sha256_ctx->buffer[0])), 0x1);
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if (ret_val != 0) {
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return ret_val;
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}
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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volatile uint32_t *output_buf = (volatile uint32_t *)output;
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for (uint32_t i = 0; i < 7; i++) {
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output_buf[i] = sys_cpu_to_be32(rts5912_sha256_ctx->state[i]);
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}
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if (rts5912_sha256_ctx->is224 == 0) {
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output_buf[7] = sys_cpu_to_be32(rts5912_sha256_ctx->state[7]);
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}
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k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
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return ret_val;
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}
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static int rts5912_sha256_handler(struct hash_ctx *ctx, struct hash_pkt *pkt, bool finish)
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{
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struct rts5912_sha256_context *rts5912_sha256_ctx =
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(struct rts5912_sha256_context *)(ctx->device)->data;
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int ret_val = 0;
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k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
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||||||
|
memcpy(rts5912_sha256_ctx->sha2_data_in_sram, pkt->in_buf, pkt->in_len);
|
||||||
|
k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
ret_val = rts5912_sha256_update(ctx->device, rts5912_sha256_ctx->sha2_data_in_sram,
|
||||||
|
pkt->in_len);
|
||||||
|
|
||||||
|
if (ret_val) {
|
||||||
|
return ret_val;
|
||||||
|
} else if (finish) {
|
||||||
|
ret_val = rts5912_sha256_finish(ctx->device, pkt->out_buf);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret_val;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rts5912_hash_begin_session(const struct device *dev, struct hash_ctx *ctx,
|
||||||
|
enum hash_algo algo)
|
||||||
|
{
|
||||||
|
struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
|
||||||
|
|
||||||
|
k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
|
||||||
|
if (rts5912_sha256_ctx->in_use == true) {
|
||||||
|
LOG_ERR("Crypto driver is busy!");
|
||||||
|
k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
return -EBUSY;
|
||||||
|
}
|
||||||
|
|
||||||
|
rts5912_sha256_ctx->in_use = true;
|
||||||
|
k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
|
||||||
|
switch (algo) {
|
||||||
|
case CRYPTO_HASH_ALGO_SHA224:
|
||||||
|
case CRYPTO_HASH_ALGO_SHA256:
|
||||||
|
k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
|
||||||
|
memset((void *)(rts5912_sha256_ctx), 0x0, sizeof(struct rts5912_sha256_context));
|
||||||
|
rts5912_sha256_ctx->is224 = (algo == CRYPTO_HASH_ALGO_SHA224);
|
||||||
|
k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
ctx->hash_hndlr = rts5912_sha256_handler;
|
||||||
|
rts5912_sha256_start(dev);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rts5912_hash_free_session(const struct device *dev, struct hash_ctx *ctx)
|
||||||
|
{
|
||||||
|
struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
|
||||||
|
|
||||||
|
k_mutex_lock(&(rts5912_sha256_ctx->crypto_rts5912_in_use), K_FOREVER);
|
||||||
|
rts5912_sha256_ctx->in_use = false;
|
||||||
|
k_mutex_unlock(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int rts5912_query_hw_caps(const struct device *dev)
|
||||||
|
{
|
||||||
|
return (CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rts5912_sha_init(const struct device *dev)
|
||||||
|
{
|
||||||
|
uint32_t ret;
|
||||||
|
struct rts5912_sha256_context *rts5912_sha256_ctx = dev->data;
|
||||||
|
uint8_t init_buf[32] = {0};
|
||||||
|
struct hash_pkt pkt = {
|
||||||
|
.in_buf = init_buf,
|
||||||
|
.out_buf = init_buf,
|
||||||
|
.in_len = 32,
|
||||||
|
.ctx = NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
k_mutex_init(&(rts5912_sha256_ctx->crypto_rts5912_in_use));
|
||||||
|
|
||||||
|
/* For Realtek crypto driver, it has to be inited by running one time
|
||||||
|
* to clear the register of the crypto driver and make sure the date in
|
||||||
|
* the driver are cleaned.
|
||||||
|
*/
|
||||||
|
|
||||||
|
ret = rts5912_hash_begin_session(dev, pkt.ctx, CRYPTO_HASH_ALGO_SHA256);
|
||||||
|
if (ret != 0) {
|
||||||
|
LOG_ERR("Crypto driver init begin fail!");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = rts5912_sha256_update(dev, pkt.in_buf, pkt.in_len);
|
||||||
|
if (ret != 0) {
|
||||||
|
LOG_ERR("Crypto driver init update fail!");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = rts5912_sha256_finish(dev, pkt.out_buf);
|
||||||
|
if (ret != 0) {
|
||||||
|
LOG_ERR("Crypto driver init finish fail!");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = rts5912_hash_free_session(dev, pkt.ctx);
|
||||||
|
if (ret != 0) {
|
||||||
|
LOG_ERR("Crypto driver init free fail!");
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static DEVICE_API(crypto, rts5912_hash_funcs) = {
|
||||||
|
.hash_begin_session = rts5912_hash_begin_session,
|
||||||
|
.hash_free_session = rts5912_hash_free_session,
|
||||||
|
.query_hw_caps = rts5912_query_hw_caps,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct rts5912_sha_config cfg_0 = {
|
||||||
|
.cfg_sha2_regs = (volatile struct sha2_type *)DT_INST_REG_ADDR_BY_NAME(0, sha2),
|
||||||
|
.cfg_sha2dma_regs = (volatile struct sha2dma_type *)DT_INST_REG_ADDR_BY_NAME(0, sha2dma),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct rts5912_sha256_context data_0;
|
||||||
|
|
||||||
|
DEVICE_DT_INST_DEFINE(0, &rts5912_sha_init, NULL, &data_0, &cfg_0, POST_KERNEL,
|
||||||
|
CONFIG_CRYPTO_INIT_PRIORITY, (void *)&rts5912_hash_funcs);
|
||||||
|
|
@ -612,6 +612,13 @@
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
sha0: crypto@40000000 {
|
||||||
|
compatible = "realtek,rts5912-sha";
|
||||||
|
reg = <0x40000000 0x40 0x40001000 932>;
|
||||||
|
reg-names = "sha2", "sha2dma";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c_0_wrapper: i2c_0_wrapper {
|
i2c_0_wrapper: i2c_0_wrapper {
|
||||||
|
|
|
||||||
18
dts/bindings/crypto/realtek,rts5912-sha.yaml
Normal file
18
dts/bindings/crypto/realtek,rts5912-sha.yaml
Normal file
|
|
@ -0,0 +1,18 @@
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
|
||||||
|
#
|
||||||
|
|
||||||
|
description: Realtek RTS5912 Crypto SHA accelerator.
|
||||||
|
|
||||||
|
compatible: "realtek,rts5912-sha"
|
||||||
|
|
||||||
|
include: base.yaml
|
||||||
|
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
required: true
|
||||||
|
|
||||||
|
reg-names:
|
||||||
|
type: string-array
|
||||||
|
required: true
|
||||||
78
soc/realtek/ec/rts5912/reg/reg_crypto.h
Normal file
78
soc/realtek/ec/rts5912/reg/reg_crypto.h
Normal file
|
|
@ -0,0 +1,78 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2025 Realtek, SIBG-SD7
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_CRYPTO_H
|
||||||
|
#define ZEPHYR_SOC_REALTEK_RTS5912_REG_CRYPTO_H
|
||||||
|
|
||||||
|
struct sha2_type {
|
||||||
|
uint32_t ctrl;
|
||||||
|
const uint32_t status;
|
||||||
|
const uint32_t reserved[2];
|
||||||
|
uint32_t digest[16];
|
||||||
|
uint32_t fifo_in;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sha2dma_type {
|
||||||
|
uint32_t sar;
|
||||||
|
const uint32_t reserved;
|
||||||
|
uint32_t dar;
|
||||||
|
const uint32_t reserved1[3];
|
||||||
|
uint32_t ctrl_low;
|
||||||
|
uint32_t ctrl_high;
|
||||||
|
const uint32_t reserved2[9];
|
||||||
|
uint32_t config;
|
||||||
|
const uint32_t reserved3[178];
|
||||||
|
uint32_t msk_transfer;
|
||||||
|
const uint32_t reserved4;
|
||||||
|
uint32_t msk_block;
|
||||||
|
const uint32_t reserved5[7];
|
||||||
|
uint32_t clear_transfer;
|
||||||
|
const uint32_t reserved6[9];
|
||||||
|
const uint32_t interrupt_status;
|
||||||
|
const uint32_t reserved7[13];
|
||||||
|
uint32_t dma_enable;
|
||||||
|
const uint32_t reserved8;
|
||||||
|
uint32_t channel_enable;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SHA_Type Start */
|
||||||
|
/* CTRL */
|
||||||
|
#define SHA2_CTRL_RST_Msk BIT(1)
|
||||||
|
#define SHA2_CTRL_DMAMD_Msk BIT(2)
|
||||||
|
#define SHA2_CTRL_BYTEINV_Msk BIT(3)
|
||||||
|
#define SHA2_CTRL_SHAMD_Msk BIT(4)
|
||||||
|
#define SHA2_CTRL_ICGEN_Msk BIT(5)
|
||||||
|
#define SHA2_CTRL_SLVMD_Msk BIT(6)
|
||||||
|
/* STS */
|
||||||
|
#define SHA2_STS_FIFOSPACE_Msk GENMASK(5, 0)
|
||||||
|
#define SHA2_STS_BUSY_Msk BIT(6)
|
||||||
|
/* SHA_Type End */
|
||||||
|
|
||||||
|
/* SHA2DMA_Type Start */
|
||||||
|
/* SHA2DMA_Type Control */
|
||||||
|
#define SHA2DMA_CTRL_INT_EN_Msk BIT(0)
|
||||||
|
#define SHA2DMA_CTRL_DST_WIDTH_Pos (1UL)
|
||||||
|
#define SHA2DMA_CTRL_SRC_WIDTH_Pos (4UL)
|
||||||
|
#define SHA2DMA_CTRL_SRC_BURST_Pos (14UL)
|
||||||
|
/* SHA2DMA_Type Enable*/
|
||||||
|
#define SHA2DMA_DMA_ENABLE_Msk BIT(0)
|
||||||
|
/* SHA2DMA_Type interrupt clear */
|
||||||
|
#define SHA2DMA_INTCLR_CLRTFR_Msk BIT(0)
|
||||||
|
/* SHA2DMA_Type mask interrupt */
|
||||||
|
#define SHA2DMA_MSKTFR_INT_EN_Msk BIT(0)
|
||||||
|
#define SHA2DMA_MSKTFR_INT_WRITE_EN_Msk BIT(8)
|
||||||
|
/* SHA2DMA_Type interrupt status */
|
||||||
|
#define SHA2DMA_INTSTS_TFR_COMPLETE_Msk BIT(0)
|
||||||
|
#define SHA2DMA_INTSTS_BLK_COMPLETE_Msk BIT(1)
|
||||||
|
#define SHA2DMA_INTSTS_SCR_COMPLETE_Msk BIT(2)
|
||||||
|
#define SHA2DMA_INTSTS_DST_COMPLETE_Msk BIT(3)
|
||||||
|
#define SHA2DMA_INTSTS_BUS_COMPLETE_Msk BIT(4)
|
||||||
|
/* SHA2DMA_Type Channel enable */
|
||||||
|
#define SHA2DMA_CHEN_EN_Msk BIT(0)
|
||||||
|
#define SHA2DMA_CHEN_WRITE_EN_Msk BIT(8)
|
||||||
|
/* SHA2DMA_Type End */
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_CRYPTO_H */
|
||||||
Loading…
Add table
Add a link
Reference in a new issue