arch: support nocache for Cortex-R52

Config NOCACHE_MEMORY depend on ARCH_HAS_NOCACHE_MEMORY_SUPPORT. Enable
ARCH_HAS_NOCACHE_MEMORY_SUPPORT for Cortex-R52 to run NXP S32Z/E with
nocache attibute.

Enable nocache in each driver use it.

Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
This commit is contained in:
Duong Vu Nam 2022-11-23 18:03:31 +07:00 committed by Carles Cufí
commit b24f4625f0
6 changed files with 6 additions and 1 deletions

View file

@ -36,6 +36,7 @@ config CPU_AARCH32_CORTEX_R
select ARCH_HAS_USERSPACE if ARM_MPU
select ARCH_HAS_EXTRA_EXCEPTION_INFO
select ARCH_HAS_CODE_DATA_RELOCATION
select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
help
This option signifies the use of a CPU of the Cortex-R family.

View file

@ -5,5 +5,6 @@ config GPIO_S32
bool "NXP S32 GPIO driver"
default y
depends on DT_HAS_NXP_S32_GPIO_ENABLED
select NOCACHE_MEMORY
help
Enable the GPIO driver for NXP S32 processors.

View file

@ -7,5 +7,6 @@ config NXP_S32_EIRQ
bool "External interrupt controller driver for NXP S32 MCUs"
default y
depends on DT_HAS_NXP_S32_SIUL2_EIRQ_ENABLED
select NOCACHE_MEMORY
help
External interrupt controller driver for NXP S32 MCUs

View file

@ -7,6 +7,7 @@ config UART_S32_LINFLEXD
depends on DT_HAS_NXP_S32_LINFLEXD_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select NOCACHE_MEMORY
help
Enable the LINFlexD UART driver for NXP S32 family processors.

View file

@ -5,6 +5,7 @@ config NXP_S32_SPI
bool "NXP S32 SPI driver"
default y
depends on DT_HAS_NXP_S32_SPI_ENABLED
select NOCACHE_MEMORY
help
Enable support for NXP S32 SPI driver.

View file

@ -93,7 +93,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: 138742f66576f2e2235a072425e71b8d1360c0d3
revision: 0ee50e0796d66307c8a99e9178140e7432b1eaba
path: modules/hal/nxp
groups:
- hal