diff --git a/soc/arm/nxp_s32/Kconfig b/soc/arm/nxp_s32/Kconfig
index 909037f5c75..a5c6ea75653 100644
--- a/soc/arm/nxp_s32/Kconfig
+++ b/soc/arm/nxp_s32/Kconfig
@@ -10,6 +10,29 @@ config SOC_FAMILY
 	string
 	default "nxp_s32"
 
+config NXP_S32_FUNC_RESET_THRESHOLD
+	int "Functional Reset Escalation threshold"
+	default 15
+	range 0 15
+	help
+	  If the value of this option is 0, the Functional reset escalation
+	  function is disabled. Any other value is the number of Functional
+	  resets that causes a Destructive reset, if the FRET register isn't
+	  written to beforehand.
+	  Default to maximum threshold (hardware reset value).
+
+config NXP_S32_DEST_RESET_THRESHOLD
+	int "Destructive Reset Escalation threshold"
+	default 0
+	range 0 15
+	help
+	  If the value of this field is 0, the Destructive reset escalation
+	  function is disabled. Any other value is the number of Destructive
+	  resets which keeps the chip in the reset state until the next power-on
+	  reset triggers a new reset sequence, if the DRET register isn't
+	  written to beforehand.
+	  Default to disabled (hardware reset value).
+
 source "soc/arm/nxp_s32/*/Kconfig.soc"
 
 config SOC_PART_NUMBER
diff --git a/soc/arm/nxp_s32/common/CMakeLists.txt b/soc/arm/nxp_s32/common/CMakeLists.txt
index 3154adc13c9..13ec5b28101 100644
--- a/soc/arm/nxp_s32/common/CMakeLists.txt
+++ b/soc/arm/nxp_s32/common/CMakeLists.txt
@@ -1,5 +1,6 @@
-# Copyright 2022 NXP
+# Copyright 2022-2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
 zephyr_sources(osif.c)
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3_M7 power_soc.c)
diff --git a/soc/arm/nxp_s32/common/power_soc.c b/soc/arm/nxp_s32/common/power_soc.c
new file mode 100644
index 00000000000..eef489ee8df
--- /dev/null
+++ b/soc/arm/nxp_s32/common/power_soc.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#ifdef CONFIG_REBOOT
+#include <zephyr/sys/reboot.h>
+#endif
+
+#include <Power_Ip.h>
+
+#ifdef CONFIG_REBOOT
+BUILD_ASSERT(POWER_IP_PERFORM_RESET_API == STD_ON, "Power Reset API must be enabled");
+
+/*
+ * Overrides default weak implementation of system reboot.
+ *
+ * SYS_REBOOT_COLD (Destructive Reset):
+ * - Leads most parts of the chip, except a few modules, to reset. SRAM content
+ *   is lost after this reset event.
+ * - Flash is always reset, so an updated value of the option bits is reloaded
+ *   in volatile registers outside of the Flash array.
+ * - Trimming is lost.
+ * - STCU is reset and configured BISTs are executed.
+ *
+ * SYS_REBOOT_WARM (Functional Reset):
+ * - Leads all the communication peripherals and cores to reset. The communication
+ *   protocols' sanity is not guaranteed and they are assumed to be reinitialized
+ *   after reset. The SRAM content, and the functionality of certain modules, is
+ *   preserved across functional reset.
+ * - The volatile registers are not reset; in case of a reset event, the
+ *   trimming is maintained.
+ * - No BISTs are executed after functional reset.
+ */
+void sys_arch_reboot(int type)
+{
+	Power_Ip_MC_RGM_ConfigType mc_rgm_cfg = { 0 };
+
+	const Power_Ip_HwIPsConfigType power_cfg = {
+		.McRgmConfigPtr = (const Power_Ip_MC_RGM_ConfigType *)&mc_rgm_cfg,
+		.PMCConfigPtr = NULL
+	};
+
+	switch (type) {
+	case SYS_REBOOT_COLD:
+		/* Destructive reset */
+		mc_rgm_cfg.ResetType = MCU_DEST_RESET;
+		Power_Ip_PerformReset(&power_cfg);
+		break;
+	case SYS_REBOOT_WARM:
+		/* Functional reset */
+		mc_rgm_cfg.ResetType = MCU_FUNC_RESET;
+		Power_Ip_PerformReset(&power_cfg);
+		break;
+	default:
+		/* Do nothing */
+		break;
+	}
+}
+#endif /* CONFIG_REBOOT */
+
+static int nxp_s32_power_init(void)
+{
+	const Power_Ip_MC_RGM_ConfigType mc_rgm_cfg = {
+		.FuncResetOpt = 0U, /* All functional reset sources enabled */
+		.FesThresholdReset = MC_RGM_FRET_FRET(CONFIG_NXP_S32_FUNC_RESET_THRESHOLD),
+		.DesThresholdReset = MC_RGM_DRET_DRET(CONFIG_NXP_S32_DEST_RESET_THRESHOLD)
+	};
+
+	const Power_Ip_PMC_ConfigType pmc_cfg = {
+#ifdef CONFIG_SOC_PART_NUMBER_S32K3
+		/* PMC Configuration Register (CONFIG) */
+		.ConfigRegister = PMC_CONFIG_LMEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMEN))
+			| PMC_CONFIG_LMBCTLEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMBCTLEN)),
+#else
+#error "SoC not supported"
+#endif
+	};
+
+	const Power_Ip_HwIPsConfigType power_cfg = {
+		.McRgmConfigPtr = &mc_rgm_cfg,
+		.PMCConfigPtr = &pmc_cfg
+	};
+
+	Power_Ip_Init(&power_cfg);
+
+	return 0;
+}
+
+SYS_INIT(nxp_s32_power_init, PRE_KERNEL_1, 1);
diff --git a/soc/arm/nxp_s32/s32k/Kconfig.soc b/soc/arm/nxp_s32/s32k/Kconfig.soc
index b2f6ddb0602..f54ffe9f903 100644
--- a/soc/arm/nxp_s32/s32k/Kconfig.soc
+++ b/soc/arm/nxp_s32/s32k/Kconfig.soc
@@ -40,4 +40,23 @@ config IVT_HEADER_SIZE
 	help
 	  Size of ivt header region
 
+config NXP_S32_PMC_LMEN
+	bool "Last Mile regulator"
+	default y if CLOCK_CONTROL
+	help
+	  Enables the Last Mile regulator, which regulates an external 1.5V
+	  voltage on V15 down to the core and logic supply (V11 power domain),
+	  which is typically 1.1V.
+	  When enabling PLL as system clock, the PMC last mile regulator should
+	  be enabled.
+
+config NXP_S32_PMC_LMBCTLEN
+	bool "External BCTL regulator for V15"
+	depends on NXP_S32_PMC_LMEN
+	help
+	  This option must be selected if an external BJT between VDD_HV_A and
+	  V15 is used on the PCB. The base of this BJT must be connected to the
+	  VRC_CTRL pin and is controlled by the PMC to regulate a voltage of
+	  1.5V on V15 pin.
+
 endif