counter: cmsdk: Add DualTimer as Counter
This patch adds Dualtimer to be used as a counter. Jira: ZEP-1300 Change-Id: Ic4a2d89ec7fc0c0c2a0bc7f6d32d97637049faaf Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit is contained in:
Vincenzo Frascino
Kumar Gala
parent
b11242d11f
commit
b1e02a594a
5 changed files with 230 additions and 0 deletions
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@ -18,4 +18,6 @@ source "drivers/counter/Kconfig.qmsi"
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source "drivers/counter/Kconfig.tmr_cmsdk_apb"
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source "drivers/counter/Kconfig.dtmr_cmsdk_apb"
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endif # COUNTER
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39
drivers/counter/Kconfig.dtmr_cmsdk_apb
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39
drivers/counter/Kconfig.dtmr_cmsdk_apb
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@ -0,0 +1,39 @@
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# Kconfig - counter configuration options
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#
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#
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# Copyright (c) 2016 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_FAMILY_ARM
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config COUNTER_DTMR_CMSDK_APB
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bool
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prompt "ARM CMSDK (Cortex-M System Design Kit) DTMR Counter driver"
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default n
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help
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The dualtimer (DTMR) present in the platform is used as a counter.
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This option enables the support for the counter.
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if COUNTER_DTMR_CMSDK_APB
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# ---------- Counter 0 ----------
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config COUNTER_DTMR_CMSDK_APB_0
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bool
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prompt "Counter 0 driver"
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default n
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help
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Enable support for Counter 0.
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config COUNTER_DTMR_CMSDK_APB_0_DEV_NAME
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string "Counter 0 Device Name"
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depends on COUNTER_DTMR_CMSDK_APB_0
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default "COUNTER_0"
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help
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Specify the device name for Counter 0 driver.
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endif # COUNTER_DTMR_CMSDK_APB
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endif # SOC_FAMILY_ARM
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@ -2,3 +2,4 @@ obj-$(CONFIG_AON_COUNTER_QMSI) += counter_qmsi_aon.o
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obj-$(CONFIG_AON_TIMER_QMSI) += counter_qmsi_aonpt.o
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obj-$(CONFIG_COUNTER_TMR_CMSDK_APB) += counter_tmr_cmsdk_apb.o
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obj-$(CONFIG_TIMER_TMR_CMSDK_APB) += timer_tmr_cmsdk_apb.o
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obj-$(CONFIG_COUNTER_DTMR_CMSDK_APB) += counter_dtmr_cmsdk_apb.o
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120
drivers/counter/counter_dtmr_cmsdk_apb.c
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120
drivers/counter/counter_dtmr_cmsdk_apb.c
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@ -0,0 +1,120 @@
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <counter.h>
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#include <device.h>
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#include <errno.h>
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#include <init.h>
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#include <soc.h>
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#include <clock_control/arm_clock_control.h>
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#include "dualtimer_cmsdk_apb.h"
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#define DUALTIMER_MAX_RELOAD 0xFFFFFFFF
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struct counter_dtmr_cmsdk_apb_cfg {
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volatile struct dualtimer_cmsdk_apb *dtimer;
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/* Dualtimer Clock control in Active State */
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const struct arm_clock_control_t dtimer_cc_as;
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/* Dualtimer Clock control in Sleep State */
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const struct arm_clock_control_t dtimer_cc_ss;
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/* Dualtimer Clock control in Deep Sleep State */
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const struct arm_clock_control_t dtimer_cc_dss;
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};
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static int counter_dtmr_cmsdk_apb_start(struct device *dev)
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{
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const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Set the dualtimer to Max reload */
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cfg->dtimer->timer1load = DUALTIMER_MAX_RELOAD;
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/* Enable the dualtimer in 32 bit mode */
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cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32);
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return 0;
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}
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static int counter_dtmr_cmsdk_apb_stop(struct device *dev)
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{
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const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Disable the dualtimer */
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cfg->dtimer->timer1ctrl = 0x0;
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return 0;
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}
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static uint32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
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{
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const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Return Counter Value */
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uint32_t value = 0;
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value = DUALTIMER_MAX_RELOAD - cfg->dtimer->timer1value;
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return value;
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}
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static int counter_dtmr_cmsdk_apb_set_alarm(struct device *dev,
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counter_callback_t callback,
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uint32_t count, void *user_data)
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{
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return -ENODEV;
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}
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static const struct counter_driver_api counter_dtmr_cmsdk_apb_api = {
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.start = counter_dtmr_cmsdk_apb_start,
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.stop = counter_dtmr_cmsdk_apb_stop,
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.read = counter_dtmr_cmsdk_apb_read,
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.set_alarm = counter_dtmr_cmsdk_apb_set_alarm,
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};
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static int counter_dtmr_cmsdk_apb_init(struct device *dev)
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{
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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struct device *clk =
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device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
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const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_as);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#else
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ARG_UNUSED(dev);
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#endif /* CONFIG_CLOCK_CONTROL */
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return 0;
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}
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/* COUNTER 0 */
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#ifdef CONFIG_COUNTER_DTMR_CMSDK_APB_0
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static const struct counter_dtmr_cmsdk_apb_cfg counter_dtmr_cmsdk_apb_cfg_0 = {
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.dtimer = ((volatile struct dualtimer_cmsdk_apb *)CMSDK_APB_DTIMER),
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.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = CMSDK_APB_DTIMER,},
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.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = CMSDK_APB_DTIMER,},
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.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = CMSDK_APB_DTIMER,},
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};
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DEVICE_AND_API_INIT(counter_dtmr_cmsdk_apb_0,
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CONFIG_COUNTER_DTMR_CMSDK_APB_0_DEV_NAME,
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counter_dtmr_cmsdk_apb_init, NULL,
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&counter_dtmr_cmsdk_apb_cfg_0, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&counter_dtmr_cmsdk_apb_api);
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#endif /* CONFIG_COUNTER_DTMR_CMSDK_APB_0 */
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68
drivers/counter/dualtimer_cmsdk_apb.h
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68
drivers/counter/dualtimer_cmsdk_apb.h
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _DRIVERS_DUALTIMER_CMSDK_AHB_
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#define _DRIVERS_DUALTIMER_CMSDK_AHB_
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#include <counter.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct dualtimer_cmsdk_apb {
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/* Offset: 0x000 (R/W) Timer 1 Load */
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volatile uint32_t timer1load;
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/* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
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volatile uint32_t timer1value;
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/* Offset: 0x008 (R/W) Timer 1 Control */
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volatile uint32_t timer1ctrl;
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/* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
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volatile uint32_t timer1intclr;
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/* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
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volatile uint32_t timer1ris;
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/* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
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volatile uint32_t timer1mis;
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/* Offset: 0x018 (R/W) Background Load Register */
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volatile uint32_t timer1bgload;
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/* Reserved */
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volatile uint32_t reserved0;
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/* Offset: 0x020 (R/W) Timer 2 Load */
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volatile uint32_t timer2load;
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/* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
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volatile uint32_t timer2value;
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/* Offset: 0x028 (R/W) Timer 2 Control */
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volatile uint32_t timer2ctrl;
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/* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
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volatile uint32_t timer2intclr;
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/* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
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volatile uint32_t timer2ris;
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/* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
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volatile uint32_t timer2mis;
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/* Offset: 0x038 (R/W) Background Load Register */
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volatile uint32_t timer2bgload;
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/* Reserved */
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volatile uint32_t reserved1[945];
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/* Offset: 0xF00 (R/W) Integration Test Control Register */
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volatile uint32_t itcr;
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/* Offset: 0xF04 ( /W) Integration Test Output Set Register */
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volatile uint32_t itop;
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};
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#define DUALTIMER_CTRL_EN (1 << 7)
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#define DUALTIMER_CTRL_MODE (1 << 6)
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#define DUALTIMER_CTRL_INTEN (1 << 5)
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#define DUALTIMER_CTRL_PRESCALE (3 << 2)
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#define DUALTIMER_CTRL_SIZE_32 (1 << 1)
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#define DUALTIMER_CTRL_ONESHOOT (1 << 0)
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#define DUALTIMER_INTCLR (1 << 0)
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#define DUALTIMER_RAWINTSTAT (1 << 0)
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#define DUALTIMER_MASKINTSTAT (1 << 0)
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVERS_DUALTIMER_CMSDK_AHB_ */
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