soc: Add support for RZ/T2M

This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>

boards/arm/rzt2m_starterkit/Kconfig.board

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZT2M_STARTER_KIT
+	bool "RZ/T2M Starter Kit Board"
+	depends on SOC_RENESAS_RZT2M

boards/arm/rzt2m_starterkit/Kconfig.defconfig

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_RZT2M_STARTER_KIT
+
+config BOARD
+	default "rzt2m_starter_kit"
+
+endif

boards/arm/rzt2m_starterkit/board.cmake

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+#
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_set_debugger_ifnset(jlink)
+board_set_flasher_ifnset(jlink)
+
+board_runner_args(jlink "--device=R9A07G075M2")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/rzt2m_starterkit/doc/index.rst

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+.. _rzt2m_starterkit:
+
+Renesas Starter Kit+ for RZ/T2M
+===============================
+
+Overview
+********
+
+The Renesas Starter Kit+ for RZ/T2M is an evaluation and development kit for the RZ/T2M MPU.
+The board is powered through a 5V input via a DC Power Jack or USB Type-C Connector.
+
+.. figure:: rzt2m_starterkit.png
+   :width: 800px
+   :align: center
+   :alt: Starter Kit+ for RZ/T2M
+
+   Starter Kit+ for RZ/T2M (Credit: Renesas)
+
+Hardware
+********
+
+The board utilizes the SoC of part no. R9A07G075M24GBG, with 2MB of RAM.
+
+It has several on-board memory components:
+* SDRAM (256MBit),
+* NOR Flash (256MBit),
+* Octa Flash (512MBit),
+* HyperRAM (512Mbit),
+* QSPI Serial Flash (512Mbit),
+* I2C EEPROM (32Kbit).
+
+The communication interfaces include:
+* Debug interfaces (J-Link, MIPI-10, MIPI-20),
+* Ethernet,
+* CAN,
+* USB,
+* RS485,
+* UART,
+* I2C,
+* SPI.
+
+Supported Features
+==================
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| PINCTRL   | on-chip    | pinctrl                             |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by the port.
+
+Connections and IOs
+===================
+
+By default, the board is configured for use with:
+* UART0 connected to the USB serial port (pins K18, K19),
+* UART3 connected to the PMOD Header (J25, pins H16, G20),
+* LEDs defined as `led0`, `led1`, `led2` and `led3`,
+
+The Zephyr console uses UART0.
+
+Programming and Debugging
+*************************
+
+Debugging
+=========
+
+Connect to the board using the J-Link On-board USB connector.
+Use `west` to start the debug server:
+
+.. code-block:: console
+
+    west debugserver
+
+Connect GDB to the server and load an application:
+
+.. code-block::
+
+    target remote :2331
+    file build/zephyr/zephyr.elf
+    load
+
+References
+**********
+
+.. _RZT2M Product page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control

boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts

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+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/renesas/rzt2m.dtsi>
+
+/ {
+	model = "RZT/2M Starter Kit";
+	compatible = "renesas,rzt2m_starter_kit";
+
+	chosen {
+		zephyr,sram = &cpu0_atcm;
+	};
+};

boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: rzt2m_starter_kit
+name: Renesas RZ/T2M Starter Kit+
+type: mcu
+arch: arm
+ram: 2048
+toolchain:
+  - zephyr
+supported:
+  - counter
+  - uart
+  - gpio
+vendor: renesas

boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_RENESAS_RZT2M=y
+CONFIG_BOARD_RZT2M_STARTER_KIT=y

dts/arm/renesas/rzt2m.dtsi

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+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "renesas,rzt2m-dev";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <1>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		compatible = "renesas,rzt2m-soc";
+
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+				<0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		cpu0_atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(512)>;
+		};
+
+		cpu0_btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(64)>;
+		};
+
+		sram0: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 DT_SIZE_M(2)>;
+		};
+
+		gsc: gsc@c0060000 {
+			/* Global System Counter */
+			compatible = "syscon";
+			reg = <0xc0060000 0x30>;
+			reg-io-width = <4>;
+		};
+
+		prcrn: prcrn@80281a10 {
+			/* Non-safety area */
+			compatible = "syscon";
+			reg = <0x80281a10 0x10>;
+			reg-io-width = <4>;
+		};
+
+		prcrs: prcrs@81281a00 {
+			/* Safety area */
+			compatible = "syscon";
+			reg = <0x81281a00 0x10>;
+			reg-io-width = <4>;
+		};
+	};
+};

soc/arm/renesas_rzt2m/CMakeLists.txt

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  )

soc/arm/renesas_rzt2m/Kconfig

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RENESAS_RZT2M
+	bool
+
+if SOC_RENESAS_RZT2M
+
+config SOC_PART_NUMBER_R9A07G075
+	bool
+
+config SOC_PART_NUMBER
+	default SOC_PART_NUMBER_R9A07G075
+
+endif # SOC_RENESAS_RZT2M

soc/arm/renesas_rzt2m/Kconfig.defconfig

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RENESAS_RZT2M
+
+config SOC
+	default "renesas_rzt2m"
+
+config NUM_IRQS
+	default 994
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default 0
+
+config FLASH_BASE_ADDRESS
+	default 0
+
+endif # SOC_RENESAS_RZT2M

soc/arm/renesas_rzt2m/Kconfig.soc

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+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RENESAS_RZT2M
+	bool "Renesas RZ/T2M MCU"
+	select ARM
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select GIC_V3
+	select GIC_SINGLE_SECURITY_STATE
+	select ARM_ARCH_TIMER
+	select SYSCON

soc/arm/renesas_rzt2m/linker.ld

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+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/cortex_r/scripts/linker.ld>

soc/arm/renesas_rzt2m/soc.c

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+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <stdint.h>
+#include <zephyr/drivers/syscon.h>
+#include "soc.h"
+#include <zephyr/sys/util_macro.h>
+
+static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
+static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
+
+void rzt2m_unlock_prcrn(uint32_t mask)
+{
+	uint32_t prcrn;
+
+	syscon_read_reg(prcrn_dev, 0, &prcrn);
+	prcrn |= PRC_KEY_CODE | mask;
+
+	syscon_write_reg(prcrn_dev, 0, prcrn);
+}
+
+void rzt2m_lock_prcrn(uint32_t mask)
+{
+	uint32_t prcrn;
+
+	syscon_read_reg(prcrn_dev, 0, &prcrn);
+	prcrn &= ~mask;
+	prcrn |= PRC_KEY_CODE;
+
+	syscon_write_reg(prcrn_dev, 0, prcrn);
+}
+
+void rzt2m_unlock_prcrs(uint32_t mask)
+{
+	uint32_t prcrs;
+
+	syscon_read_reg(prcrs_dev, 0, &prcrs);
+	prcrs |= PRC_KEY_CODE | mask;
+
+	syscon_write_reg(prcrs_dev, 0, prcrs);
+}
+
+void rzt2m_lock_prcrs(uint32_t mask)
+{
+	uint32_t prcrs;
+
+	syscon_read_reg(prcrs_dev, 0, &prcrs);
+	prcrs &= ~mask;
+	prcrs |= PRC_KEY_CODE;
+
+	syscon_write_reg(prcrs_dev, 0, prcrs);
+}
+
+void rzt2m_enable_counters(void)
+{
+	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
+
+	syscon_write_reg(dev, 0, CNTCR_EN);
+}
+
+static int rzt2m_init(void)
+{
+	/* Unlock the Protect Registers
+	 * so that device drivers can access configuration registers of peripherals.
+	 */
+	/* After the device drivers are done, lock the Protect Registers. */
+
+	rzt2m_enable_counters();
+	return 0;
+}
+
+SYS_INIT(rzt2m_init, PRE_KERNEL_1, 0);

soc/arm/renesas_rzt2m/soc.h

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+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+/* Do not let CMSIS to handle GIC and Timer */
+#include <stdint.h>
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+
+/* Global system counter */
+#define CNTCR_EN   BIT(0)
+#define CNTCR_HDBG BIT(1)
+
+/* Safety area protect register */
+#define PRCRS_CLK       BIT(0)
+#define PRCRS_LPC_RESET BIT(1)
+#define PRCRS_GPIO      BIT(2)
+#define PRCRS_SYS_CTRL  BIT(3)
+
+/* Non-safety area protect register */
+#define PRCRN_PRC0 BIT(0)
+#define PRCRN_PRC1 BIT(1)
+#define PRCRN_PRC2 BIT(2)
+
+/* PRC Key Code - this value is required to allow any write operation
+ * to the PRCRS / PRCRN registers.
+ * See section 10.2 of the RZ/T2M User's Manual: Hardware.
+ */
+#define PRC_KEY_CODE 0xa500
+
+void rzt2m_unlock_prcrn(uint32_t mask);
+void rzt2m_lock_prcrn(uint32_t mask);
+void rzt2m_unlock_prcrs(uint32_t mask);
+void rzt2m_lock_prcrs(uint32_t mask);
+
+#endif /* _SOC__H_ */