From b15f942684c807cc5a97e68c02ac6066e08d69ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Sat, 7 Jun 2025 21:24:05 +0200 Subject: [PATCH] drivers: intc_wch_pfic: correct/optimize interrupt disable logic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The IRER registers are write-only and clear the enable bit for the provided interrupt. Use a direct write instead of a read/modify/write sequence to avoid generating a bogus read access and improve performance Signed-off-by: Benjamin Cabé --- drivers/interrupt_controller/intc_wch_pfic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/interrupt_controller/intc_wch_pfic.c b/drivers/interrupt_controller/intc_wch_pfic.c index 8626b28e178..fa07f6cbcd7 100644 --- a/drivers/interrupt_controller/intc_wch_pfic.c +++ b/drivers/interrupt_controller/intc_wch_pfic.c @@ -23,7 +23,7 @@ void arch_irq_enable(unsigned int irq) void arch_irq_disable(unsigned int irq) { - PFIC->IRER[irq / 32] |= 1 << (irq % 32); + PFIC->IRER[irq / 32] = 1 << (irq % 32); } int arch_irq_is_enabled(unsigned int irq)