arch: arm: aarch32: Split fault_s.S for Cortex-M and the rest
The exception/fault handling mechanisms for the ARM Cortex-M and the rest (i.e. Cortex-A and Cortex-R) are significantly different and there is no benefit in having the two implementations in the same file. This commit relocates the Cortex-M fault handler to `cortex_m/fault_s.S` and the Cortex-A/-R generic exception handler to `cortex_a_r/exc.S` (note that the Cortex-A and Cortex-R architectures do not provide direct fault vectors; instead, they provide the exception vectors that can be used to handle faults). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis
Carles Cufí
parent
37f44193f3
commit
b14d53435b
5 changed files with 70 additions and 45 deletions
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@ -12,7 +12,6 @@ zephyr_library_sources(
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irq_manage.c
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thread.c
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cpu_idle.S
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fault_s.S
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fatal.c
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nmi.c
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nmi_on_reset.S
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@ -5,6 +5,7 @@ zephyr_library()
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zephyr_library_sources(
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vector_table.S
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reset.S
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exc.S
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exc_exit.S
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fault.c
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irq_init.c
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58
arch/arm/core/aarch32/cortex_a_r/exc.S
Normal file
58
arch/arm/core/aarch32/cortex_a_r/exc.S
Normal file
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@ -0,0 +1,58 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Exception handlers for ARM Cortex-A and Cortex-R
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*
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* Exception handlers for ARM Cortex-A and Cortex-R processors.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <offsets_short.h>
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#include <arch/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(z_arm_fault_undef_instruction)
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GTEXT(z_arm_fault_prefetch)
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GTEXT(z_arm_fault_data)
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GTEXT(z_arm_undef_instruction)
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GTEXT(z_arm_prefetch_abort)
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GTEXT(z_arm_data_abort)
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/**
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*
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* @brief Generic exception handler
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*
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* A generic exception handler that simply invokes z_arm_fault() with currently
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* unused arguments.
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*
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* Provides these symbols:
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*
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* z_arm_undef_instruction
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* z_arm_prefetch_abort
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* z_arm_data_abort
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*/
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SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_undef_instruction)
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SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_prefetch_abort)
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SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_data_abort)
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/*
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* Pass null for the esf to z_arm_fault for now. A future PR will add
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* better exception debug for Cortex-R that subsumes what esf
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* provides.
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*/
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mov r0, #0
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bl z_arm_fault
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pop {r0, lr}
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subs pc, lr, #8
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.end
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@ -5,6 +5,7 @@ zephyr_library()
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zephyr_library_sources(
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vector_table.S
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reset.S
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fault_s.S
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fault.c
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exc_exit.S
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scb.c
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@ -7,9 +7,9 @@
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/**
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* @file
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* @brief Fault handlers for ARM Cortex-M and Cortex-R
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* @brief Fault handlers for ARM Cortex-M
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*
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* Fault handlers for ARM Cortex-M and Cortex-R processors.
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* Fault handlers for ARM Cortex-M processors.
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*/
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#include <toolchain.h>
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@ -20,7 +20,6 @@ _ASM_FILE_PROLOGUE
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GTEXT(z_arm_fault)
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GTEXT(z_arm_hard_fault)
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#if defined(CONFIG_CPU_CORTEX_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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@ -31,34 +30,25 @@ GTEXT(z_arm_usage_fault)
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GTEXT(z_arm_secure_fault)
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#endif /* CONFIG_ARM_SECURE_FIRMWARE*/
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GTEXT(z_arm_debug_monitor)
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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GTEXT(z_arm_exc_spurious)
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#elif defined(CONFIG_CPU_CORTEX_R)
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GTEXT(z_arm_undef_instruction)
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GTEXT(z_arm_prefetch_abort)
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GTEXT(z_arm_data_abort)
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GTEXT(z_arm_reserved)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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GTEXT(z_arm_exc_spurious)
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/**
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*
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* @brief Fault handler installed in the fault and reserved vectors
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* @brief Fault handler installed in the fault vectors
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*
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* Entry point for the HardFault, MemManageFault, BusFault, UsageFault,
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* SecureFault, Debug Monitor, and reserved exceptions.
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* SecureFault and Debug Monitor exceptions.
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*
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* For Cortex-M: the function supplies the values of
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* The function supplies the values of
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* - the MSP
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* - the PSP
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* - the EXC_RETURN value
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* as parameters to the z_arm_fault() C function that will perform the
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* rest of the fault handling (i.e. z_arm_fault(MSP, PSP, EXC_RETURN)).
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*
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* For Cortex-R: the function simply invokes z_arm_fault() with currently
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* unused arguments.
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*
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* Provides these symbols:
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*
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* z_arm_hard_fault
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@ -68,11 +58,9 @@ GTEXT(z_arm_reserved)
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* z_arm_secure_fault
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* z_arm_debug_monitor
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* z_arm_exc_spurious
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* z_arm_reserved
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_hard_fault)
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#if defined(CONFIG_CPU_CORTEX_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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@ -83,41 +71,19 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_usage_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_secure_fault)
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_debug_monitor)
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)
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#elif defined(CONFIG_CPU_CORTEX_R)
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_undef_instruction)
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_prefetch_abort)
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_data_abort)
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_reserved)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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SECTION_SUBSEC_FUNC(TEXT,__fault,z_arm_exc_spurious)
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#if defined(CONFIG_CPU_CORTEX_M)
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mrs r0, MSP
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mrs r1, PSP
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mov r2, lr /* EXC_RETURN */
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push {r0, lr}
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#elif defined(CONFIG_CPU_CORTEX_R)
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/*
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* Pass null for the esf to z_arm_fault for now. A future PR will add
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* better exception debug for Cortex-R that subsumes what esf
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* provides.
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*/
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mov r0, #0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE || CONFIG_ARMv7_M_ARMV8_M_MAINLINE */
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bl z_arm_fault
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#if defined(CONFIG_CPU_CORTEX_M)
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pop {r0, pc}
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#elif defined(CONFIG_CPU_CORTEX_R)
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pop {r0, lr}
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subs pc, lr, #8
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#endif
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.end
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