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drivers: rtwdog: add NXP rtwdog driver

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Port NXP rtwdog driver to Zephyr.

Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
This commit is contained in:
Ruijia Wang 2024-12-02 22:02:44 +08:00 • committed by Benjamin Cabé
commit b1395eabce
7 changed files with 324 additions and 0 deletions
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2
boards/nxp/mimxrt1180_evk/doc/index.rst
View file

@ -124,6 +124,8 @@ configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| RTWDOG | on-chip | rtwdog |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`

1
boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
View file

@ -26,4 +26,5 @@ supported:
- i3c
- dma
- spi
- watchdog
vendor: nxp

1
drivers/watchdog/CMakeLists.txt
View file

@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT8XXX2 wdt_ite_it8xxx2.c)
zephyr_library_sources_ifdef(CONFIG_WDT_LITEX wdt_litex.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MAX32 wdt_max32.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_IMX_WDOG wdt_mcux_imx_wdog.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_RTWDOG wdt_mcux_rtwdog.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG wdt_mcux_wdog.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG32 wdt_mcux_wdog32.c)
zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WWDT wdt_mcux_wwdt.c)

7
drivers/watchdog/Kconfig.mcux
View file

@ -37,3 +37,10 @@ config WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG
the number of watchdog counter ticks before timeout.
endif # WDT_MCUX_WWDT
config WDT_MCUX_RTWDOG
bool "MCUX RTWDOG driver"
default y
depends on DT_HAS_NXP_RTWDOG_ENABLED
help
Enable the mcux rtwdog driver.

225
drivers/watchdog/wdt_mcux_rtwdog.c Normal file
View file

@ -0,0 +1,225 @@
/*
* Copyright 2024, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_rtwdog
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/watchdog.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys_clock.h>
#include <fsl_rtwdog.h>
#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(wdt_mcux_rtwdog);
#define MSEC_TO_RTWDOG_TICKS(clock_freq, divider, msec) \
((uint32_t)(clock_freq * msec / 1000U / divider))
#define RTWDOG_MIN_TIMEOUT 1U
struct mcux_rtwdog_config {
RTWDOG_Type *base;
uint32_t clock_frequency;
rtwdog_clock_source_t clk_source;
rtwdog_clock_prescaler_t clk_divider;
void (*irq_config_func)(const struct device *dev);
};
struct mcux_rtwdog_data {
wdt_callback_t callback;
rtwdog_config_t wdog_config;
bool timeout_valid;
bool enabled;
};
static int mcux_rtwdog_setup(const struct device *dev, uint8_t options)
{
const struct mcux_rtwdog_config *config = dev->config;
struct mcux_rtwdog_data *data = dev->data;
RTWDOG_Type *base = config->base;
if (!data->timeout_valid) {
LOG_ERR("No valid timeouts installed");
return -EINVAL;
}
if (data->enabled) {
LOG_ERR("This watchdog has been enabled");
return -EBUSY;
}
if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0U) {
LOG_ERR("Not support WDT_OPT_PAUSE_IN_SLEEP");
return -ENOTSUP;
}
data->wdog_config.workMode.enableDebug = ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U);
RTWDOG_Init(base, &data->wdog_config);
data->enabled = true;
LOG_DBG("Setup the watchdog");
return 0;
}
static int mcux_rtwdog_disable(const struct device *dev)
{
const struct mcux_rtwdog_config *config = dev->config;
struct mcux_rtwdog_data *data = dev->data;
RTWDOG_Type *base = config->base;
data->timeout_valid = false;
if (!data->enabled) {
LOG_ERR("Disabled when watchdog is not enabled");
return -EFAULT;
}
RTWDOG_Deinit(base);
data->enabled = false;
LOG_DBG("Disabled the watchdog");
return 0;
}
static int mcux_rtwdog_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
{
const struct mcux_rtwdog_config *config = dev->config;
struct mcux_rtwdog_data *data = dev->data;
uint32_t clock_freq;
uint32_t clk_divider;
if (data->enabled) {
LOG_ERR("Timeout can not be installed while watchdog has already been setup");
return -EBUSY;
}
if (data->timeout_valid) {
LOG_ERR("No more timeouts can be installed");
return -ENOMEM;
}
if (cfg->flags == WDT_FLAG_RESET_NONE) {
LOG_ERR("Not support WDT_FLAG_RESET_NONE");
return -ENOTSUP;
}
RTWDOG_GetDefaultConfig(&data->wdog_config);
clock_freq = config->clock_frequency;
clk_divider = config->clk_divider == kRTWDOG_ClockPrescalerDivide1 ? 1U : 256U;
data->wdog_config.clockSource = config->clk_source;
data->wdog_config.prescaler = config->clk_divider;
data->wdog_config.timeoutValue =
MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.max);
if (data->wdog_config.timeoutValue > UINT16_MAX) {
LOG_ERR("Invalid window max");
return -EINVAL;
}
if (cfg->window.min != 0U) {
data->wdog_config.enableWindowMode = true;
data->wdog_config.windowValue =
MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.min);
} else {
data->wdog_config.enableWindowMode = false;
data->wdog_config.windowValue = 0;
}
if ((data->wdog_config.timeoutValue < RTWDOG_MIN_TIMEOUT) ||
(data->wdog_config.timeoutValue <= data->wdog_config.windowValue)) {
LOG_ERR("Invalid timeout");
return -EINVAL;
}
data->wdog_config.enableInterrupt = cfg->callback != NULL;
data->callback = cfg->callback;
data->timeout_valid = true;
return 0;
}
static int mcux_rtwdog_feed(const struct device *dev, int channel_id)
{
const struct mcux_rtwdog_config *config = dev->config;
struct mcux_rtwdog_data *data = dev->data;
RTWDOG_Type *base = config->base;
if (channel_id != 0) {
LOG_ERR("Invalid channel id");
return -EINVAL;
}
if (!data->enabled) {
LOG_ERR("Feed disabled watchdog");
return -EINVAL;
}
RTWDOG_Refresh(base);
LOG_DBG("Fed the watchdog");
return 0;
}
static void mcux_rtwdog_isr(const struct device *dev)
{
const struct mcux_rtwdog_config *config = dev->config;
struct mcux_rtwdog_data *data = dev->data;
RTWDOG_Type *base = config->base;
RTWDOG_ClearStatusFlags(base, kRTWDOG_InterruptFlag);
if (data->callback) {
data->callback(dev, 0);
}
}
static int mcux_rtwdog_init(const struct device *dev)
{
const struct mcux_rtwdog_config *config = dev->config;
config->irq_config_func(dev);
return 0;
}
static DEVICE_API(wdt, mcux_rtwdog_api) = {
.setup = mcux_rtwdog_setup,
.disable = mcux_rtwdog_disable,
.install_timeout = mcux_rtwdog_install_timeout,
.feed = mcux_rtwdog_feed,
};
#define TO_RTWDOG_CLK_SRC(val) _DO_CONCAT(kRTWDOG_ClockSource, val)
#define TO_RTWDOG_CLK_DIV(val) _DO_CONCAT(kRTWDOG_ClockPrescalerDivide, val)
#define MCUX_RTWDOG_INIT(n) \
\
static struct mcux_rtwdog_data mcux_rtwdog_data_##n; \
static void mcux_rtwdog_config_func_##n(const struct device *dev); \
\
static const struct mcux_rtwdog_config mcux_rtwdog_config_##n = { \
.base = (RTWDOG_Type *)DT_INST_REG_ADDR(n), \
.irq_config_func = mcux_rtwdog_config_func_##n, \
.clock_frequency = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
.clk_source = TO_RTWDOG_CLK_SRC(DT_INST_PROP(n, clk_source)), \
.clk_divider = TO_RTWDOG_CLK_DIV(DT_INST_PROP(n, clk_divider)), \
}; \
static void mcux_rtwdog_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_rtwdog_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}; \
DEVICE_DT_INST_DEFINE(n, &mcux_rtwdog_init, NULL, &mcux_rtwdog_data_##n, \
&mcux_rtwdog_config_##n, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_rtwdog_api);
DT_INST_FOREACH_STATUS_OKAY(MCUX_RTWDOG_INIT)

60
dts/arm/nxp/nxp_rt118x.dtsi
View file

@ -11,6 +11,10 @@
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
aliases {
watchdog0 = &rtwdog0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -74,6 +78,12 @@
compatible = "nxp,imx-ccm-rev2";
reg = <0x4450000 0x4000>;
#clock-cells = <3>;
lpo: lpo32k {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
lpuart1: uart@4380000 {
@ -1070,6 +1080,56 @@
#address-cells = <1>;
#size-cells = <0>;
};
rtwdog0: wdog@42d0000 {
compatible = "nxp,rtwdog";
reg = <0x42d0000 0x10>;
status = "okay";
interrupts = <38 0>;
clocks = <&lpo>;
clk-source = <1>;
clk-divider = <1>;
};
rtwdog1: wdog@42e0000 {
compatible = "nxp,rtwdog";
reg = <0x42e0000 0x10>;
status = "disabled";
interrupts = <39 0>;
clocks = <&lpo>;
clk-source = <1>;
clk-divider = <1>;
};
rtwdog2: wdog@2490000 {
compatible = "nxp,rtwdog";
reg = <0x2490000 0x10>;
status = "disabled";
interrupts = <79 0>;
clocks = <&lpo>;
clk-source = <1>;
clk-divider = <1>;
};
rtwdog3: wdog@24a0000 {
compatible = "nxp,rtwdog";
reg = <0x24a0000 0x10>;
status = "disabled";
interrupts = <80 0>;
clocks = <&lpo>;
clk-source = <1>;
clk-divider = <1>;
};
rtwdog4: wdog@24b0000 {
compatible = "nxp,rtwdog";
reg = <0x24b0000 0x10>;
status = "disabled";
interrupts = <81 0>;
clocks = <&lpo>;
clk-source = <1>;
clk-divider = <1>;
};
};
&flexspi {

28
dts/bindings/watchdog/nxp,rtwdog.yaml Normal file
View file

@ -0,0 +1,28 @@
# Copyright 2024, NXP
# SPDX-License-Identifier: Apache-2.0
description: NXP RT watchdog
compatible: "nxp,rtwdog"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true
clocks:
required: true
clk-source:
type: int
required: true
description: Watchdog counter clock source
clk-divider:
type: int
description: Watchdog counter clock divider
required: true