arch: common: be able to use ROM_START_OFFSET on RISCV

be able to use ROM_START_OFFSET on RISCV.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

arch/common/CMakeLists.txt

@@ -76,9 +76,8 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
   nocache.ld
 )
 
-# Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
+# Only ARM, X86 and RISCV use ROM_START_OFFSET.
-if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
+if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 OR DEFINED CONFIG_RISCV)
-    OR DEFINED CONFIG_SOC_OPENISA_RV32M1)
   # Exclamation mark is printable character with lowest number in ASCII table.
   # We are sure that this file will be included as a first.
   zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld)

soc/lowrisc/opentitan/Kconfig.defconfig

@@ -18,4 +18,9 @@ config 2ND_LVL_INTR_00_OFFSET
 config NUM_IRQS
 	default 256
 
+# The OpenTitan SoC requires a manifest in front of the
+# application binary.
+config ROM_START_OFFSET
+	default 0x404
+
 endif # SOC_OPENTITAN

tests/kernel/smp/testcase.yaml

@@ -31,6 +31,9 @@ tests:
       - smp
     ignore_faults: true
     filter: (CONFIG_MP_MAX_NUM_CPUS > 1)
+    platform_exclude:
+      - qemu_riscv64/qemu_virt_riscv64/smp # qemu_riscv64 doesn't support custom ROM offset
+      - qemu_riscv32/qemu_virt_riscv32/smp # qemu_riscv32 doesn't support custom ROM offset
     extra_configs:
       - CONFIG_SCHED_CPU_MASK=y
       - CONFIG_ROM_START_OFFSET=0x80