arch: xtensa: save/restore HiFi AudioEngine regs

Adds the necessary code required to unconditionally save/restore the
HiFi AE registers. The macros xchal_cp1_load and xchal_cp1_store
are defined in the Xtensa HAL.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>

arch/xtensa/core/CMakeLists.txt

@@ -27,6 +27,7 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c)
 zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
 zephyr_library_sources_ifdef(CONFIG_SMP smp.c)
+zephyr_library_sources_ifdef(CONFIG_XTENSA_HIFI_SHARING xtensa_hifi.S)
 
 zephyr_library_sources_ifdef(
   CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK

arch/xtensa/core/userspace.S

@@ -87,6 +87,10 @@ end_loop:
 	s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
 	ODD_REG_SAVE
 
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+	call0 _xtensa_hifi_save
+#endif
+
 	call0 xtensa_save_high_regs
 
 	l32i a2, a1, 0

arch/xtensa/core/xtensa_asm2_util.S

@@ -160,6 +160,11 @@ _restore_context:
 	FPU_REG_RESTORE
 #endif
 
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+.extern _xtensa_hifi_load
+	call0 _xtensa_hifi_load
+#endif
+
 	l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
 	wsr a0, SAR
 #if XCHAL_HAVE_LOOPS
@@ -248,6 +253,10 @@ xtensa_switch:
 	movi a0, _switch_restore_pc
 	s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
 
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+	call0 _xtensa_hifi_save
+#endif
+
 	/* Now the high registers */
 	call0 xtensa_save_high_regs
 

arch/xtensa/core/xtensa_hifi.S

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <offsets.h>
+
+#include <xtensa/config/tie.h>
+#include <xtensa/config/tie-asm.h>
+
+/*
+ * Load the HiFi registers from the hifi buffer in the BSA. Round the address
+ * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary
+ * alignment.
+ *
+ * Upon entry ...
+ * A0 - return address (do not modify)
+ * A1 - address of BSA (do not modify)
+ * A2 - available for use
+ * A3 - available for use
+ */
+.global _xtensa_hifi_load
+.align 4
+_xtensa_hifi_load:
+        addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
+        movi a3, ~(XCHAL_CP1_SA_ALIGN - 1)
+        and a2, a2, a3
+
+        xchal_cp1_load a2 a3 a3 a3 a3    /* Only A2 and A3 are used by macro */
+
+	ret
+
+/*
+ * Save the HiFi registers into the hifi buffer in the BSA. Round the address
+ * of this buffer up to XCHAL_CP1_SA_ALIGN bytes to guarantee the necessary
+ * alignment.
+ *
+ * A0 - return address (do not modify)
+ * A1 - address of BSA (do not modify)
+ * A2 - available for use
+ * A3 - available for use
+ */
+.global _xtensa_hifi_save
+.align 4
+_xtensa_hifi_save:
+        addi a2, a1, (___xtensa_irq_bsa_t_hifi_OFFSET + XCHAL_CP1_SA_ALIGN - 1)
+        movi a3, ~(XCHAL_CP1_SA_ALIGN - 1)
+        and a2, a2, a3
+
+        xchal_cp1_store a2 a3 a3 a3 a3  /* Only A2 and A3 are used by macro */
+
+	ret

arch/xtensa/include/xtensa_asm2_s.h

@@ -16,6 +16,10 @@
  * only by the assembler.
  */
 
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+.extern _xtensa_hifi_save
+#endif
+
 /*
  * SPILL_ALL_WINDOWS
  *
@@ -184,6 +188,7 @@
 #if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
 	FPU_REG_SAVE
 #endif
+
 .endm
 
 #ifdef CONFIG_XTENSA_MMU
@@ -405,6 +410,11 @@ _xstack_returned_\@:
 	s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
 
 	ODD_REG_SAVE
+
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+	call0 _xtensa_hifi_save    /* Save HiFi registers */
+#endif
+
 	call0 xtensa_save_high_regs
 
 	l32i a2, a1, 0